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* Retry: "Emit CodeView type records for nested classes."Adrian McCarthy2016-07-061-0/+98
| | | | | | | | | | Now with a corrected test to account for a recently supported properties bit in the debug info of a struct. Original review: http://reviews.llvm.org/D21939 This reverts commit 970c3fd497a28d25dd69526eb52594a696c37968. llvm-svn: 274661
* [DSE] Avoid iterator invalidation bugs.Chad Rosier2016-07-061-83/+0
| | | | | | | | | | The dse_with_dbg_value.ll test committed with r273141 is removed because this we no longer performs any type of back tracking, which is what was causing the codegen differences with and without debug information. Differential Revision: http://reviews.llvm.org/D21613 llvm-svn: 274660
* [x86] fix cost of SINT_TO_FP for i32 --> float (PR21356, PR28434)Sanjay Patel2016-07-061-6/+6
| | | | | | | | | | | | | This is "cvtdq2ps" which does not appear to be particularly slow on any CPU according to Agner's tables. Choosing "5" as a cost here as suggested in: https://llvm.org/bugs/show_bug.cgi?id=21356 ...but it seems very conservative given that the instruction is fully pipelined, and I think these costs are supposed to model throughput. Note that related costs are also most likely too high, but this fixes PR21356 and partly fixes PR28434. llvm-svn: 274658
* Work around PR28400 a bit harder.Sean Silva2016-07-061-0/+19
| | | | | | | | | | We were still crashing in the "no change" case because LVI was not getting invalidated. See the thread "Should analyses be able to hold AssertingVH to IR? (related to PR28400)" for more discussion. llvm-svn: 274656
* [SystemZ] Remove AND mask of bottom 6 bits when result is used for shift/rotateElliot Colp2016-07-063-2/+194
| | | | | | | | | | On SystemZ, shift and rotate instructions only use the bottom 6 bits of the shift/rotate amount. Therefore, if the amount is ANDed with an immediate mask that has all of the bottom 6 bits set, we can remove the AND operation entirely. Differential Revision: http://reviews.llvm.org/D21854 llvm-svn: 274650
* [pdb] Round trip the PDB stream between YAML and binary PDB.Zachary Turner2016-07-062-6/+64
| | | | | | This gets writing of the PDB stream working. llvm-svn: 274647
* Ensure all uses of permute instructions feed vector storesKit Barton2016-07-061-0/+55
| | | | | | | | | | | | | | | There is a problem in VSXSwapRemoval where it is incorrectly removing permute instructions. In this case, the permute is feeding both a vector store and also a non-store instruction. In this case, the permute cannot be removed. The fix is to simply look at all the uses of the vector register defined by the permute and ensure that all the uses are vector store instructions. This problem was reported in PR 27735 (https://llvm.org/bugs/show_bug.cgi?id=27735). Test case based on the original problem reported. Phabricator Review: http://reviews.llvm.org/D21802 llvm-svn: 274645
* [DAGCombiner] Fix visitSTORE to continue processing current SDNode, if ↵Tim Shen2016-07-061-0/+70
| | | | | | | | | | | | | | | | | findBetterNeighborChains doesn't actually CombineTo it. Summary: findBetterNeighborChains may or may not find a better chain for each node it finds, which include the node ("St") that visitSTORE is currently processing. If no better chain is found for St, visitSTORE should continue instead of return SDValue(St, 0), as if it's CombinedTo'ed. This fixes bug 28130. There might be other ways to make the test pass (see D21409). I think both of the patches are fixing actual bugs revealed by the same testcase. Reviewers: echristo, wschmidt, hfinkel, kbarton, amehsan, arsenm, nemanjai, bogner Subscribers: mehdi_amini, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D21692 llvm-svn: 274644
* [TTI] The cost model should not assume vector casts get completely scalarizedMichael Kuperstein2016-07-065-213/+213
| | | | | | | | | | | | | | | | The cost model should not assume vector casts get completely scalarized, since on targets that have vector support, the common case is a partial split up to the legal vector size. So, when a vector cast gets split, the resulting casts end up legal and cheap. Instead of pessimistically assuming scalarization, base TTI can use the costs the concrete TTI provides for the split vector, plus a fudge factor to account for the cost of the split itself. This fudge factor is currently 1 by default, except on AMDGPU where inserts and extracts are considered free. Differential Revision: http://reviews.llvm.org/D21251 llvm-svn: 274642
* Revert "Emit CodeView type records for nested classes."Adrian McCarthy2016-07-061-98/+0
| | | | | | This reverts commit 256b29322c827a2d94da56468c936596f5509032. llvm-svn: 274632
* [X86][SSE] Added test cases for missed opportunities to combine pshufb to ↵Simon Pilgrim2016-07-063-0/+82
| | | | | | pslldq/psrldq llvm-svn: 274631
* Emit CodeView type records for nested classes.Adrian McCarthy2016-07-061-0/+98
| | | | | | Differential Revision: http://reviews.llvm.org/D21939 llvm-svn: 274629
* [LV] Don't widen trivial induction variablesMatthew Simpson2016-07-064-16/+198
| | | | | | | | | | | | | | | | | | | | We currently always vectorize induction variables. However, if an induction variable is only used for counting loop iterations or computing addresses with getelementptr instructions, we don't need to do this. Vectorizing these trivial induction variables can create vector code that is difficult to simplify later on. This is especially true when the unroll factor is greater than one, and we create vector arithmetic when computing step vectors. With this patch, we check if an induction variable is only used for counting iterations or computing addresses, and if so, scalarize the arithmetic when computing step vectors instead. This allows for greater simplification. This patch addresses the suboptimal pointer arithmetic sequence seen in PR27881. Reference: https://llvm.org/bugs/show_bug.cgi?id=27881 Differential Revision: http://reviews.llvm.org/D21620 llvm-svn: 274627
* Re-commit of 274613.Elena Demikhovsky2016-07-0610-287/+290
| | | | | | | The prev commit failed on compilation. A minor change in one pattern in lib/Target/X86/X86InstrAVX512.td fixes the failure. llvm-svn: 274626
* [AMDGPU] Assembler: regression tests for bug 28413. NFCSam Kolton2016-07-063-10/+36
| | | | llvm-svn: 274623
* [ARM] Do not test for CPUs, use SubtargetFeatures. Also remove 2 flags.Diana Picus2016-07-061-1/+1
| | | | | | | | | | | | | | | This is a follow-up for r273544. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. This commit also removes two command-line flags that weren't used in any of the tests: widen-vmovs and swift-partial-update-clearance. The former may be easily replaced with the mattr mechanism, but the latter may not (as it is a subtarget property, and not a proper feature). Differential Revision: http://reviews.llvm.org/D21797 llvm-svn: 274620
* Reverted 274613 due to compilation failue. Elena Demikhovsky2016-07-0610-290/+287
| | | | llvm-svn: 274615
* AVX-512: Optimization for patterns with i1 scalar typeElena Demikhovsky2016-07-0610-287/+290
| | | | | | | | | | | | | | The patch removes redundant kmov instructions (not all, we still have a lot of work here) and redundant "and" instructions after "setcc". I use "AssertZero" marker between X86ISD::SETCC node and "truncate" to eliminate extra "and $1" instruction. I also changed zext, aext and trunc patterns in the .td file. It allows to remove extra "kmov" instruictions. This patch fixes https://llvm.org/bugs/show_bug.cgi?id=28173. Fast ISEL mode is not supported correctly for AVX-512. ICMP/FCMP scalar instruction should return result in k-reg. It will be fixed in one of the next patches. I redirected handling of "cmp" to the DAG builder mode. (The code looks worse in one specific test case, but without this fix the new patch fails). Differential revision: http://reviews.llvm.org/D21956 llvm-svn: 274613
* AMDGPU: Fix return of non-void-returning shadersNicolai Haehnle2016-07-061-1/+2
| | | | | | | | | | | | | | | | | Summary: Since "AMDGPU: Fix verifier errors in SILowerControlFlow", the logic that ensures that a non-void-returning shader falls off the end of the last basic block was effectively disabled, since SI_RETURN is now used. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96731 Reviewers: arsenm, tstellarAMD Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D21975 llvm-svn: 274612
* Vector GEP test: renamed + some commentsElena Demikhovsky2016-07-061-1/+8
| | | | | | Differential revision: http://reviews.llvm.org/D21957 llvm-svn: 274611
* Fix handling of forward unreachable but reverse-reachable blocks in ↵Daniel Berlin2016-07-061-0/+23
| | | | | | MemorySSA construction llvm-svn: 274606
* [CFLAA] Split into Anders+Steens analysis.George Burgess IV2016-07-0634-62/+62
| | | | | | | | | | | | | | | | | | | | | StratifiedSets (as implemented) is very fast, but its accuracy is also limited. If we take a more aggressive andersens-like approach, we can be way more accurate, but we'll also end up being slower. So, we've decided to split CFLAA into CFLSteensAA and CFLAndersAA. Long-term, we want to end up in a place where CFLSteens is queried first; if it can provide an answer, great (since queries are basically map lookups). Otherwise, we'll fall back to CFLAnders, BasicAA, etc. This patch splits everything out so we can try to do something like that when we get a reasonable CFLAnders implementation. Patch by Jia Chen. Differential Revision: http://reviews.llvm.org/D21910 llvm-svn: 274589
* [asan] Add a hidden option for Mach-O global metadata liveness trackingRyan Govostes2016-07-051-1/+1
| | | | llvm-svn: 274578
* AArch64: TableGenerate system instruction operands.Tim Northover2016-07-056-39/+39
| | | | | | | | | | | | | | | | | | | | The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. llvm-svn: 274576
* Revert r259387: "AArch64: Implement missed conditional compare sequences."Balaram Makam2016-07-051-67/+12
| | | | | | | This reverts commit r259387 because it inserts illegal code after legalization in some backends where i64 OR type is illegal for example. llvm-svn: 274573
* [X86][AVX2] Add support for target shuffle combining to BROADCASTSimon Pilgrim2016-07-052-0/+154
| | | | | | Only support broadcast from vector register so far - memory folding support will have to wait. llvm-svn: 274572
* [X86][AVX512] Fixed decoding of permd/permpd variable mask shuffles + ↵Simon Pilgrim2016-07-051-0/+49
| | | | | | | | enabled them for target shuffle combining Corrected element mask masking to extract the bottom index bits (now matches the perm2 implementation but for unary inputs). llvm-svn: 274571
* ARM: fix `-mlong-calls` for WoASaleem Abdulrasool2016-07-051-1/+1
| | | | | | | | | Not all code-paths set the relocation model to static for Windows. This currently breaks on Windows ARM with `-mlong-calls` when built with clang. Loosen the assertion to what it was previously. We would ideally ensure that all the configuration sets Windows to static relocation model. llvm-svn: 274570
* DAGCombiner: Fold away vector extract of insert with the same indexMatt Arsenault2016-07-051-0/+66
| | | | | | | This only really matters when the index is non-constant since the constant case already gets taken care of by other combines. llvm-svn: 274569
* AArch64: use correct SDValue # when looking for bitfield placement.Tim Northover2016-07-051-0/+36
| | | | | | | | | | The other use really does only care about the SDNode (it checks the opcode against a whitelist), but bitFieldPlacement can be misled if the node produces multiple results. Patch by Ismail Badawi. llvm-svn: 274567
* AMDGPU: Fix folding SGPRs into madak/madmk src0Matt Arsenault2016-07-051-0/+29
| | | | | | | | | | Because of the special immediate operand, the constant bus is already used so SGPRs are never useful. r263212 changed the name of the immediate operand, which broke the verifier check for the restriction. llvm-svn: 274564
* [AMDGPU] Assembler: Fix parsing error with floating-point literals passed to ↵Sam Kolton2016-07-052-0/+18
| | | | | | | | integer instructions Differential Revision: http://reviews.llvm.org/D21972 llvm-svn: 274551
* [X86][AVX512] Autoupgrade the BROADCAST intrinsicsSimon Pilgrim2016-07-056-343/+347
| | | | llvm-svn: 274550
* [X86][AVX512BW] Added BROADCAST intrinsics fast-isel generic IR testsSimon Pilgrim2016-07-052-0/+364
| | | | llvm-svn: 274545
* [Thumb] Reapply r272251 with a fix for PR28348 (mk 2)James Molloy2016-07-052-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | The important thing I was missing was ensuring newly added constants were kept in topological order. Repositioning the node is correct if the constant is newly added (so it has no topological ordering) but wrong if it already existed - positioning it next in the worklist would break the topological ordering. Original commit message: [Thumb] Select a BIC instead of AND if the immediate can be encoded more optimally negated If an immediate is only used in an AND node, it is possible that the immediate can be more optimally materialized when negated. If this is the case, we can negate the immediate and use a BIC instead; int i(int a) { return a & 0xfffffeec; } Used to produce: ldr r1, [CONSTPOOL] ands r0, r1 CONSTPOOL: 0xfffffeec And now produces: movs r1, #255 adds r1, #20 ; Less costly immediate generation bics r0, r1 llvm-svn: 274543
* [X86][AVX512] Added BROADCAST intrinsics fast-isel generic IR testsSimon Pilgrim2016-07-052-18/+795
| | | | llvm-svn: 274537
* [PowerPC] - Legalize vector types by widening instead of integer promotionNemanja Ivanovic2016-07-055-46/+82
| | | | | | | | | | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D20443 It changes the legalization strategy for illegal vector types from integer promotion to widening. This only applies for vectors with elements of width that is a multiple of a byte since we have hardware support for vectors with 1, 2, 3, 8 and 16 byte elements. Integer promotion for vectors is quite expensive on PPC due to the sequence of breaking apart the vector, extending the elements and reconstituting the vector. Two of these operations are expensive. This patch causes between minor and major improvements in performance on most benchmarks. There are very few benchmarks whose performance regresses. These regressions can be handled in a subsequent patch with a DAG combine (similar to how this patch handles int -> fp conversions of illegal vector types). llvm-svn: 274535
* [X86][AVX512] Added VSHUFPD intrinsics fast-isel generic IR testsSimon Pilgrim2016-07-051-0/+52
| | | | llvm-svn: 274534
* [X86][AVX512VL] Added VSHUFPD/VSHUFPS intrinsics fast-isel generic IR testsSimon Pilgrim2016-07-051-0/+274
| | | | llvm-svn: 274533
* test: relax the match on the timestampSaleem Abdulrasool2016-07-051-1/+1
| | | | llvm-svn: 274529
* Object: support empty UID/GID fieldsSaleem Abdulrasool2016-07-052-0/+5
| | | | | | | | | Normal archives do not have empty UID/GID fields. However, the Microsoft Import library format is a customized archive (it just uses an alternate symbol index format). When the import library is constructed by lib.exe, the UID and GID fields are left empty. Do not abort on such an input. llvm-svn: 274528
* [X86][AVX512] Add support for lowering shuffles to VSHUFPDSimon Pilgrim2016-07-042-8/+3
| | | | llvm-svn: 274520
* Revert "[Thumb] Reapply r272251 with a fix for PR28348"James Molloy2016-07-042-29/+0
| | | | | | This reverts commit r274510 - it made green dragon unhappy. llvm-svn: 274512
* [Thumb] Reapply r272251 with a fix for PR28348James Molloy2016-07-042-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | We were using DAG->getConstant instead of DAG->getTargetConstant. This meant that we could inadvertently increase the use count of a constant if stars aligned, which it did in this testcase. Increasing the use count of the constant could cause ISel to fall over (because DAGToDAG lowering assumed the constant had only one use!) Original commit message: [Thumb] Select a BIC instead of AND if the immediate can be encoded more optimally negated If an immediate is only used in an AND node, it is possible that the immediate can be more optimally materialized when negated. If this is the case, we can negate the immediate and use a BIC instead; int i(int a) { return a & 0xfffffeec; } Used to produce: ldr r1, [CONSTPOOL] ands r0, r1 CONSTPOOL: 0xfffffeec And now produces: movs r1, #255 adds r1, #20 ; Less costly immediate generation bics r0, r1 llvm-svn: 274510
* [X86][AVX512] Autoupgrade the VPERMPD/VPERMQ intrinsicsSimon Pilgrim2016-07-044-85/+86
| | | | llvm-svn: 274506
* [X86][AVX512] Added VPERMPD/VPERMQ intrinsics fast-isel generic IR testsSimon Pilgrim2016-07-042-0/+252
| | | | llvm-svn: 274503
* [X86][AVX512] Autoupgrade the VPERMILPD/VPERMILPS intrinsicsSimon Pilgrim2016-07-044-136/+136
| | | | llvm-svn: 274498
* [X86][AVX512] Added VPERMILPD/VPERMILPS intrinsics fast-isel generic IR testsSimon Pilgrim2016-07-041-0/+163
| | | | | | Added PSHUFD tests as well llvm-svn: 274493
* Add writeonly IR attributeNicolai Haehnle2016-07-0410-22/+60
| | | | | | | | | | | | | | | | | Summary: This complements the earlier addition of IntrWriteMem and IntrWriteArgMem LLVM intrinsic properties, see D18291. Also start using the attribute for memset, memcpy, and memmove intrinsics, and remove their special-casing in BasicAliasAnalysis. Reviewers: reames, joker.eph Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D18714 llvm-svn: 274485
* [CodeGen] Make the code that detects a if a shuffle is really a ↵Craig Topper2016-07-041-6/+0
| | | | | | | | | | concatenation of the inputs more general purpose. We can now handle concatenation of each source multiple times. The previous code just checked for each source to appear once in either order. This also now handles an entire source vector sized piece having undef indices correctly. We now concat with UNDEF instead of using one of the sources. This is responsible for the test case change. llvm-svn: 274483
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