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| author | Sam Kolton <Sam.Kolton@amd.com> | 2016-07-05 14:01:11 +0000 |
|---|---|---|
| committer | Sam Kolton <Sam.Kolton@amd.com> | 2016-07-05 14:01:11 +0000 |
| commit | a9cd6aa895f7740cb7a125f3f45201c6402a6f4c (patch) | |
| tree | 2a14b25d6d14a38328b9dd896f0c72cfea97ac50 /llvm/test | |
| parent | 4e96fbf3c1a8b44656f31b35632b84a91edc3d85 (diff) | |
| download | bcm5719-llvm-a9cd6aa895f7740cb7a125f3f45201c6402a6f4c.tar.gz bcm5719-llvm-a9cd6aa895f7740cb7a125f3f45201c6402a6f4c.zip | |
[AMDGPU] Assembler: Fix parsing error with floating-point literals passed to integer instructions
Differential Revision: http://reviews.llvm.org/D21972
llvm-svn: 274551
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/MC/AMDGPU/vop1.s | 10 | ||||
| -rw-r--r-- | llvm/test/MC/AMDGPU/vop2.s | 8 |
2 files changed, 18 insertions, 0 deletions
diff --git a/llvm/test/MC/AMDGPU/vop1.s b/llvm/test/MC/AMDGPU/vop1.s index 22a4f91afef..e82206a7ada 100644 --- a/llvm/test/MC/AMDGPU/vop1.s +++ b/llvm/test/MC/AMDGPU/vop1.s @@ -374,3 +374,13 @@ v_sin_f16 v1, v2 // NOSICI: v_cos_f16 v1, v2 // VI: v_cos_f16_e32 v1, v2 ; encoding: [0x02,0x95,0x02,0x7e] v_cos_f16 v1, v2 + +//===----------------------------------------------------------------------===// +// Floating point literals +//===----------------------------------------------------------------------===// + +// GCN: v_mov_b32_e32 v0, 0.5 ; encoding: [0xf0,0x02,0x00,0x7e] +v_mov_b32 v0, 0.5 + +// GCN: v_mov_b32_e32 v0, 0x40480000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x00,0x48,0x40] +v_mov_b32 v0, 3.125
\ No newline at end of file diff --git a/llvm/test/MC/AMDGPU/vop2.s b/llvm/test/MC/AMDGPU/vop2.s index 0cb464ac949..b4a19fee290 100644 --- a/llvm/test/MC/AMDGPU/vop2.s +++ b/llvm/test/MC/AMDGPU/vop2.s @@ -94,6 +94,14 @@ v_mul_i32_i24 v1, s2, 3 // SICI: v_mul_i32_i24_e64 v1, 3, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x83,0x06,0x00,0x00] v_mul_i32_i24 v1, 3, s3 +// SICI: v_add_i32_e32 v0, vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x00,0x4a] +// VI: v_add_i32_e32 v0, vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x00,0x32] +v_add_i32 v0, vcc, 0.5, v0 + +// SICI: v_add_i32_e32 v0, vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x00,0x4a,0x00,0x00,0x48,0x40] +// VI: v_add_i32_e32 v0, vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x00,0x32,0x00,0x00,0x48,0x40] +v_add_i32 v0, vcc, 3.125, v0 + //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// |
