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* [Power9]Legalize and emit code for converting (Un)Signed Word to Quad-PrecisionLei Huang2018-04-181-1/+160
| | | | | | | | | | | Legalize and emit code for converting (Un)Signed Word to quad-precision via: xscvsdqp xscvudqp Differential Revision: https://reviews.llvm.org/D45389 llvm-svn: 330273
* [DEBUG] Initial adaptation of NVPTX target for debug info emission.Alexey Bataev2018-04-183-28/+8676
| | | | | | | | | | | | | | | Summary: Patch adds initial emission of the debug info for NVPTX target. Currently, only .file and .loc directives are emitted, everything else is commented out to not break the compilation of Cuda. Reviewers: echristo, jlebar, tra, jholewinski Subscribers: mgorny, aprantl, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D41827 llvm-svn: 330271
* [x86] Switch EFLAGS copy lowering to use reg-reg form of testing forChandler Carruth2018-04-186-31/+31
| | | | | | | | | | | | | | | | a zero register. Previously I tried this and saw LLVM unable to transform this to fold with memory operands such as spill slot rematerialization. However, it clearly works as shown in this patch. We turn these into `cmpb $0, <mem>` when useful for folding a memory operand without issue. This form has no disadvantage compared to `testb $-1, <mem>`. So overall, this is likely no worse and may be slightly smaller in some cases due to the `testb %reg, %reg` form. Differential Revision: https://reviews.llvm.org/D45475 llvm-svn: 330269
* Fix macosx build broken by r330249Pavel Labath2018-04-182-4/+41
| | | | | | | | | | | | | It seems llc crashes when targetting darwin with split-dwarf (pr37164). This happens on all inputs, not just the one I added in the above commit. Work around the issue by hardcoding the target triple to linux, which is what all split-dwarf tests seem to be doing. As I don't know of a way to specify the os part of the triple without spelling out the architecture as well, I move the new test to the X86 folder. llvm-svn: 330265
* [x86] Fix PR37100 by teaching the EFLAGS copy lowering to rewrite usesChandler Carruth2018-04-183-0/+110
| | | | | | | | | | | | | | | | | | | | | | across basic blocks in the limited cases where it is very straight forward to do so. This will also be useful for other places where we do some limited EFLAGS propagation across CFG edges and need to handle copy rewrites afterward. I think this is rapidly approaching the maximum we can and should be doing here. Everything else begins to require either heroic analysis to prove how to do PHI insertion manually, or somehow managing arbitrary PHI-ing of EFLAGS with general PHI insertion. Neither of these seem at all promising so if those cases come up, we'll almost certainly need to rewrite the parts of LLVM that produce those patterns. We do now require dominator trees in order to reliably diagnose patterns that would require PHI nodes. This is a bit unfortunate but it seems better than the completely mysterious crash we would get otherwise. Differential Revision: https://reviews.llvm.org/D45673 llvm-svn: 330264
* [llvm-link] Use WithColor for printing errorsJonas Devlieghere2018-04-185-11/+11
| | | | | | | | Use convenience helpers in WithColor to print errors and warnings. Differential revision: https://reviews.llvm.org/D45667 llvm-svn: 330261
* [SimplifyLibcalls] Realloc(null, N) -> Malloc(N)Sanjay Patel2018-04-181-0/+24
| | | | | | | | Patch by Dávid Bolvanský! Differential Revision: https://reviews.llvm.org/D45413 llvm-svn: 330259
* [AMDGPU] Fix issues for backend divergence trackingDavid Stuttard2018-04-182-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: A change to use divergence analysis in the AMDGPU backend was getting formal arguments incorrect (not tagged as divergent) unless they were VGPR0, VGPR1 or VGPR2 For graphics shaders it is possible to have more than these passed in as VGPR Modified the checking code to check for any VGPR registers passed in as formal arguments. Also, some intrinsics that are sources of divergence may have been lowered during instruction selection and are missed on subsequent calls to isSDNodeSourceOfDivergence - added the relevant AMDGPUISD checks as well. Finally, the FunctionLoweringInfo tracks virtual registers that are live across basic block boundaries. This is used to check for divergence of CopyFromRegister registers using the DivergenceAnalysis analysis. For multiple blocks the lazily evaluated inverted map VirtReg2Value was not cleared when the ValueMap map was. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45372 Change-Id: I112f3bd6dfe0f62e63ce9b43b893982778e4bee3 llvm-svn: 330257
* [IRCE] Only check for NSW on equality predicatesSam Parker2018-04-181-6/+18
| | | | | | | | | | | After investigation discussed in D45439, it would seem that the nsw flag restriction is unnecessary in most cases. So the IsInductionVar lambda has been removed, the functionality extracted, and now only require nsw when using eq/ne predicates. Differential Revision: https://reviews.llvm.org/D45617 llvm-svn: 330256
* Add tests for shrink wrapping and VLAsMomchil Velikov2018-04-182-0/+189
| | | | | | Differential revision: https://reviews.llvm.org/D45727 llvm-svn: 330253
* [gold] Add support for optimization remarksTeresa Johnson2018-04-181-0/+76
| | | | | | | | | | | | | | Summary: Adds support for LTO opt remarks (optionally with hotness) to gold-plugin. Reviewers: anemet Subscribers: fhahn, mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D45752 llvm-svn: 330252
* [LoopUnroll] Only peel if a predicate becomes known in the loop body.Florian Hahn2018-04-181-128/+141
| | | | | | | | | | | | | If a predicate does not become known after peeling, peeling is unlikely to be beneficial. Reviewers: mcrosier, efriedma, mkazantsev, junbuml Reviewed By: mkazantsev Differential Revision: https://reviews.llvm.org/D44983 llvm-svn: 330250
* [CodeGen/Dwarf] Make debug_names compatible with split-dwarfPavel Labath2018-04-181-0/+4
| | | | | | | | | | | | | | | | | | Summary: Previously we crashed for the combination of the two features because we tried to reference the dwo CU from the main object file. The fix consists of two items: - reference the skeleton CU from the name index (the consumer is expected to use the skeleton CU to find the real data). - use the main object file string pool for the strings in the index Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45566 llvm-svn: 330249
* [UpdateTestChecks] Add update_mca_test_checks.py scriptGreg Bedwell2018-04-1834-166/+1025
| | | | | | | | | | | This script can be used to regenerate tests in the test/tools/llvm-mca directory (PR36904). Regenerated a number of tests using the pattern: test/tools/llvm-mca/*/*/*.s Differential Revision: https://reviews.llvm.org/D45369 llvm-svn: 330246
* [DebugInfo] Sink related dbg users when sinking in InstCombineBjorn Pettersson2018-04-182-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When sinking an instruction in InstCombine we now also sink the DbgInfoIntrinsics that are using the sunken value. Example) When sinking the load in this input bb.X: %0 = load i64, i64* %start, align 4, !dbg !31 tail call void @llvm.dbg.value(metadata i64 %0, ...) br i1 %cond, label %for.end, label %for.body.lr.ph for.body.lr.ph: br label %for.body we now also move the dbg.value, like this bb.X: br i1 %cond, label %for.end, label %for.body.lr.ph for.body.lr.ph: %0 = load i64, i64* %start, align 4, !dbg !31 tail call void @llvm.dbg.value(metadata i64 %0, ...) br label %for.body In the past we haven't moved the dbg.value so we got bb.X: tail call void @llvm.dbg.value(metadata i64 %0, ...) br i1 %cond, label %for.end, label %for.body.lr.ph for.body.lr.ph: %0 = load i64, i64* %start, align 4, !dbg !31 br label %for.body So in the past we got a debug-use before the def of %0. And that dbg.value was also on the path jumping to %for.end, for which %0 never was defined. CodeGenPrepare normally comes to rescue later (when not moving the dbg.value), since it moves dbg.value instrinsics quite brutally, without really analysing if it is correct to move the intrinsic (see PR31878). So at the moment this patch isn't expected to have much impact, besides that it is moving the dbg.value already in opt, making the IR look more sane directly. This can be seen as a preparation to (hopefully) make it possible to turn off CodeGenPrepare::placeDbgValues later as a solution to PR31878. I also adjusted test/DebugInfo/X86/sdagsplit-1.ll to make the IR in the test case up-to-date with this behavior in InstCombine. Reviewers: rnk, vsk, aprantl Reviewed By: vsk, aprantl Subscribers: mattd, JDevlieghere, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D45425 llvm-svn: 330243
* [X86] Give CMOV 2 cycle latency on SLM.Craig Topper2018-04-181-180/+180
| | | | llvm-svn: 330239
* [X86] Don't crash on bad operand modifiers in inline assemblyCraig Topper2018-04-181-0/+8
| | | | | | | | | | | | | | Summary: Previously if a modifer was placed on a non-GPR register class we would hit an assert or crash. Reviewers: echristo Reviewed By: echristo Subscribers: eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D45751 llvm-svn: 330238
* [InstCombine] peek through bitcasted vector/array pointer GEP operandSanjay Patel2018-04-181-0/+20
| | | | | | | | | | | | | | The bitcast may be interfering with other combines or vectorization as shown in PR16739: https://bugs.llvm.org/show_bug.cgi?id=16739 Most pointer-related optimizations are probably able to look through this bitcast, but removing the bitcast shrinks the IR, so it's at least a size savings. Differential Revision: https://reviews.llvm.org/D44833 llvm-svn: 330237
* [AMDGPU] Enabled v2.16 literals for VOP3PStanislav Mekhanoshin2018-04-1712-56/+49
| | | | | | | | Literal encoding needs op_sel_hi to select low 16 bit in this case. Differential Revision: https://reviews.llvm.org/D45745 llvm-svn: 330230
* [Mem2Reg] Create merged debug locations for inserted phisVedant Kumar2018-04-171-0/+110
| | | | | | | | | | | | | | | | | | | | | | Track the debug locations of the incoming values to newly-created phis, and apply merged debug locations to the phis. A merged location will be on line 0, but will have the correct scope set. This improves crash reporting when an inlined instruction with a merged location triggers a machine exception. A debugger will be able to narrow down the crash to the correct inlined scope, instead of simply pointing to the outer scope of the caller. Taken together with a change allows generating merged line-0 locations for instructions which aren't calls, this results in a 0.5% increase in the uncompressed size of the .debug_line section of a stage2+Release build of clang (-O3 -g). rdar://33858697 Differential Revision: https://reviews.llvm.org/D45397 llvm-svn: 330227
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-179-134/+270
| | | | | | | | | | | | | | The implementation follows the MIPS backend and expands the pseudo instruction directly during asm parsing. As the result, only real MC instructions are emitted to the MCStreamer. Additionally, PseudoLI instructions are emitted during codegen. The actual expansion to real instructions is performed during MI to MC lowering and is similar to the expansion performed by the GNU Assembler. Differential Revision: https://reviews.llvm.org/D41949 Patch by Mario Werner. llvm-svn: 330224
* LoadStoreVectorizer crashes due to unsized typeStanislav Mekhanoshin2018-04-171-0/+16
| | | | | | | | | When we skip bitcasts while looking for GEP in LoadSoreVectorizer we should also verify that the type is sized otherwise we assert Differential Revision: https://reviews.llvm.org/D45709 llvm-svn: 330221
* [XRay] Typed event logging intrinsicKeith Wyss2018-04-172-2/+47
| | | | | | | | | | | | | | | | | | | | | Summary: Add an LLVM intrinsic for type discriminated event logging with XRay. Similar to the existing intrinsic for custom events, but also accepts a type tag argument to allow plugins to be aware of different types and semantically interpret logged events they know about without choking on those they don't. Relies on a symbol defined in compiler-rt patch D43668. I may wait to submit before I can see demo everything working together including a still to come clang patch. Reviewers: dberris, pelikan, eizan, rSerge, timshen Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45633 llvm-svn: 330219
* [WebAssembly] Teach fast-isel to gracefully recover from illegal return types.Dan Gohman2018-04-171-0/+16
| | | | | | Fixes PR36564. llvm-svn: 330215
* [llvm-pdbutil] Dump first section contribution for each module.Zachary Turner2018-04-171-0/+5
| | | | | | | | | | | | | | The DBI stream contains a list of module descriptors. At the beginning of each descriptor is a structure representing the first section contribution in the output file for that module. LLD currently doesn't fill out this structure at all, but link.exe does. So as a precursor to emitting this data in LLD, we first need a way to dump it so that it can be checked. This patch adds support for the dumping, and verifies via a test that LLD emits bogus information. llvm-svn: 330208
* [X86] Add separate scheduling class for PSADBW instruction.Craig Topper2018-04-174-25/+21
| | | | llvm-svn: 330204
* [X86] Remove -mcpu=skx/knl from some tests and use -mattr instead.Craig Topper2018-04-173-33/+34
| | | | | | mcpu exposes other tuning flags. These tests are only trying to test instruction set features so it is better to use mattr. llvm-svn: 330196
* Revert "Fix incorrect choice of callee-saved registers save/restore points ↵Momchil Velikov2018-04-171-114/+0
| | | | | | | | | (take 2)" Revert in order to fix the test to not run when required targets aren't configured. llvm-svn: 330193
* Fix incorrect choice of callee-saved registers save/restore points (take 2)Momchil Velikov2018-04-171-0/+114
| | | | | | | | Add the accidentally omitted testcase. Differential revision: https://reviews.llvm.org/D45524 llvm-svn: 330192
* [Hexagon] Do not merge initializers for stack and non-stack expressionsKrzysztof Parzyszek2018-04-171-0/+35
| | | | | | | | | Stack addressing needs addressing modes that provide an offset field immediately following the frame index. An initializer from a non-stack addressing could force the stack address to use a form that does not provide an offset field. llvm-svn: 330191
* [PowerPC] Mark the BDNZ intrinsic as NoDuplicateNemanja Ivanovic2018-04-171-0/+75
| | | | | | | | | | | | | Duplicating this intrinsic is not generally valid because it has the side-effect of decrementing the CTR. Any passes that duplicate it would need to be taught to keep the regions formed completely disjoint. This patch should be NFC for typical uses as CTRLoops runs after the remaining loop passes. It only affects situations where the loop passes are scheduled on the IR after the codegen passes (as is the case with some JIT pipelines). Fixes https://bugs.llvm.org/show_bug.cgi?id=37050 llvm-svn: 330186
* Revert "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." again."Michael Zolotukhin2018-04-171-28/+0
| | | | | | This reverts r330175. There are still stage3/stage4 miscompares. llvm-svn: 330180
* [X86] Add FP comparison scheduler classesSimon Pilgrim2018-04-171-12/+12
| | | | | | | | Split VCMP/VMAX/VMIN instructions off to WriteFCmp and VCOMIS instructions off to WriteFCom instead of assuming they match WriteFAdd Differential Revision: https://reviews.llvm.org/D45656 llvm-svn: 330179
* [DAGCombiner] Fix for oss-fuzz bugGerolf Hoflehner2018-04-171-0/+53
| | | | llvm-svn: 330178
* Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." again.Michael Zolotukhin2018-04-171-0/+28
| | | | | | | | | One more, hopefully the last, bug is fixed: when forming UsesToRewrite we should ignore phi operands coming from edges that we want to delete. This reverts r329910. llvm-svn: 330175
* [IR] Upgrade comment token in objc retain release marker for asm callGerolf Hoflehner2018-04-172-0/+9
| | | | | | Older compiler issued '#' instead of ';' llvm-svn: 330173
* [DebugInfo] Follow-up bug fix on "Fixing a couple of DI duplication bugs of ↵Roman Tereshin2018-04-161-0/+41
| | | | | | | | | | | | CloneModule" Apparently, DebugInfoFinder::processCompileUnit doesn't process all of the possible kinds of DIImportedEntit'ies, e.g. DIGlobalVariable's. Previously introduced `llvm_unreachable` is therefore incorrect. Removing it here. llvm-svn: 330167
* [X86] Remove unnecessary -mattr to enable avx512bw when the -mcpu already ↵Craig Topper2018-04-161-1/+1
| | | | | | | | enabled it. NFC This makes the test similar to the arith-sub.ll and arith-mul.ll tests. llvm-svn: 330144
* [SLP] Use getExtractWithExtendCost() to compute the scalar cost of ↵Haicheng Wu2018-04-161-16/+69
| | | | | | | | | | | | | extractelement/ext pair We use getExtractWithExtendCost to calculate the cost of extractelement and s|zext together when computing the extract cost after vectorization, but we calculate the cost of extractelement and s|zext separately when computing the scalar cost which is larger than it should be. Differential Revision: https://reviews.llvm.org/D45469 llvm-svn: 330143
* [CodeView] Initial support for emitting S_THUNK32 symbols for compiler...Brock Wyma2018-04-161-0/+586
| | | | | | | | | | | When emitting CodeView debug information, compiler-generated thunk routines should be emitted using S_THUNK32 symbols instead of S_GPROC32_ID symbols so Visual Studio can properly step into the user code. This initial support only handles standard thunk ordinals. Differential Revision: https://reviews.llvm.org/D43838 llvm-svn: 330132
* [InstCombine] simplify fneg+fadd folds; NFCSanjay Patel2018-04-162-24/+27
| | | | | | | | Two cleanups: 1. As noted in D45453, we had tests that don't need FMF that were misplaced in the 'fast-math.ll' test file. 2. This removes the final uses of dyn_castFNegVal, so that can be deleted. We use 'match' now. llvm-svn: 330126
* [AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32Dmitry Preobrazhensky2018-04-165-1/+41
| | | | | | | | | See bug 36356: https://bugs.llvm.org/show_bug.cgi?id=36356 Differential Revision: https://reviews.llvm.org/D45446 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 330123
* [test] Avoid spurious failure in debug-names-find.s. NFC.Pavel Labath2018-04-161-3/+3
| | | | | | | Have llvm-dwarfdump take input from stdin to avoid leaking the host paths into the tests, causing nondeterministic failures. llvm-svn: 330121
* [AArch64][SVE] Asm: Support for structured LD4 (scalar+imm) load instructions.Sander de Smalen2018-04-168-0/+372
| | | | | | | | | | | | Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45624 llvm-svn: 330120
* [AArch64][SVE] Asm: Support for structured LD3 (scalar+imm) load instructions.Sander de Smalen2018-04-168-0/+372
| | | | | | | | | | | | Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45623 llvm-svn: 330116
* [MIR-Canon] Fixing a test failure caused by COPY Folding.Puyan Lotfi2018-04-161-3/+1
| | | | llvm-svn: 330115
* [mips] Restrict certain trap instructions for micromipsr6Stefan Maksimovic2018-04-161-0/+6
| | | | | | | | | Instructions removed from micromipsr6: teqi, tgei, tgeiu, tlti, tltiu, tnei Differential Revision: https://reviews.llvm.org/D45318 llvm-svn: 330114
* [MIR-Canon] Adding ISA-Agnostic COPY Folding.Puyan Lotfi2018-04-161-0/+45
| | | | | | | | | | | | | | | | | Transforms the following: %vreg1234:gpr32 = COPY %42 %vreg1235:gpr32 = COPY %vreg1234 %vreg1236:gpr32 = COPY %vreg1235 $w0 = COPY %vreg1236 into: $w0 = COPY %42 Assuming %42 is also a gpr32 llvm-svn: 330113
* [X86] Introduce archs: goldmont-plus & tremontGabor Buella2018-04-161-0/+2
| | | | | | | | | | | | | | | Using Goldmont's cost tables for these two upcoming atom archs. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45612 llvm-svn: 330109
* [AArch64][SVE] Asm: Support for structured LD2 (scalar+imm) load instructions.Sander de Smalen2018-04-168-0/+372
| | | | | | | | | | | | Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45622 llvm-svn: 330108
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