[AArch64][SVE] Asm: Support for structured LD3 (scalar+imm) load instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45623

llvm-svn: 330116

8 files changed, 372 insertions, 0 deletions

diff --git a/llvm/test/MC/AArch64/SVE/ld3b-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld3b-diagnostics.s
new file mode 100644
index 00000000000..d07dafad5e1
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld3b-diagnostics.s
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-24, 21].
+
+ld3b {z12.b, z13.b, z14.b}, p4/z, [x12, #-27, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3b {z12.b, z13.b, z14.b}, p4/z, [x12, #-27, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3b {z7.b, z8.b, z9.b}, p3/z, [x1, #24, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3b {z7.b, z8.b, z9.b}, p3/z, [x1, #24, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of three.
+
+ld3b {z12.b, z13.b, z14.b}, p4/z, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3b {z12.b, z13.b, z14.b}, p4/z, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3b {z7.b, z8.b, z9.b}, p3/z, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3b {z7.b, z8.b, z9.b}, p3/z, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+ld3b {z2.b, z3.b, z4.b}, p8/z, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld3b {z2.b, z3.b, z4.b}, p8/z, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld3b { }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld3b { }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld3b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3b { z0.b, z1.b, z2.h }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: ld3b { z0.b, z1.b, z2.h }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3b { z0.b, z1.b, z3.b }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: ld3b { z0.b, z1.b, z3.b }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3b { v0.16b, v1.16b, v2.16b }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld3b { v0.16b, v1.16b, v2.16b }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld3b.s b/llvm/test/MC/AArch64/SVE/ld3b.s
new file mode 100644
index 00000000000..748f59cad83
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld3b.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld3b    { z0.b, z1.b, z2.b }, p0/z, [x0]
+// CHECK-INST: ld3b    { z0.b, z1.b, z2.b }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x40,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 40 a4 <unknown>
+
+ld3b    { z23.b, z24.b, z25.b }, p3/z, [x13, #-24, mul vl]
+// CHECK-INST: ld3b    { z23.b, z24.b, z25.b }, p3/z, [x13, #-24, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0x48,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed 48 a4 <unknown>
+
+ld3b    { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl]
+// CHECK-INST: ld3b    { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0x45,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 45 a4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld3d-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld3d-diagnostics.s
new file mode 100644
index 00000000000..96f17217de2
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld3d-diagnostics.s
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-24, 21].
+
+ld3d {z12.d, z13.d, z14.d}, p4/z, [x12, #-27, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3d {z12.d, z13.d, z14.d}, p4/z, [x12, #-27, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3d {z7.d, z8.d, z9.d}, p3/z, [x1, #24, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3d {z7.d, z8.d, z9.d}, p3/z, [x1, #24, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of three.
+
+ld3d {z12.d, z13.d, z14.d}, p4/z, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3d {z12.d, z13.d, z14.d}, p4/z, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3d {z7.d, z8.d, z9.d}, p3/z, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3d {z7.d, z8.d, z9.d}, p3/z, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+ld3d {z2.d, z3.d, z4.d}, p8/z, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld3d {z2.d, z3.d, z4.d}, p8/z, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld3d { }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld3d { }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld3d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3d { z0.d, z1.d, z2.b }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: ld3d { z0.d, z1.d, z2.b }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3d { z0.d, z1.d, z3.d }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: ld3d { z0.d, z1.d, z3.d }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3d { v0.2d, v1.2d, v2.2d }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld3d { v0.2d, v1.2d, v2.2d }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld3d.s b/llvm/test/MC/AArch64/SVE/ld3d.s
new file mode 100644
index 00000000000..332c0ddaf8c
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld3d.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld3d    { z0.d, z1.d, z2.d }, p0/z, [x0]
+// CHECK-INST: ld3d    { z0.d, z1.d, z2.d }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0xc0,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 c0 a5 <unknown>
+
+ld3d    { z23.d, z24.d, z25.d }, p3/z, [x13, #-24, mul vl]
+// CHECK-INST: ld3d    { z23.d, z24.d, z25.d }, p3/z, [x13, #-24, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0xc8,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed c8 a5 <unknown>
+
+ld3d    { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl]
+// CHECK-INST: ld3d    { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0xc5,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 c5 a5 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld3h-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld3h-diagnostics.s
new file mode 100644
index 00000000000..545a96dac41
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld3h-diagnostics.s
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-24, 21].
+
+ld3h {z12.h, z13.h, z14.h}, p4/z, [x12, #-27, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3h {z12.h, z13.h, z14.h}, p4/z, [x12, #-27, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3h {z7.h, z8.h, z9.h}, p3/z, [x1, #24, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3h {z7.h, z8.h, z9.h}, p3/z, [x1, #24, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of three.
+
+ld3h {z12.h, z13.h, z14.h}, p4/z, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3h {z12.h, z13.h, z14.h}, p4/z, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3h {z7.h, z8.h, z9.h}, p3/z, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3h {z7.h, z8.h, z9.h}, p3/z, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+ld3h {z2.h, z3.h, z4.h}, p8/z, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld3h {z2.h, z3.h, z4.h}, p8/z, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld3h { }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld3h { }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld3h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3h { z0.h, z1.h, z2.s }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: ld3h { z0.h, z1.h, z2.s }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3h { z0.h, z1.h, z3.h }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: ld3h { z0.h, z1.h, z3.h }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3h { v0.8h, v1.8h, v2.8h }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld3h { v0.8h, v1.8h, v2.8h }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld3h.s b/llvm/test/MC/AArch64/SVE/ld3h.s
new file mode 100644
index 00000000000..3de35f6ba33
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld3h.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld3h    { z0.h, z1.h, z2.h }, p0/z, [x0]
+// CHECK-INST: ld3h    { z0.h, z1.h, z2.h }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0xc0,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 c0 a4 <unknown>
+
+ld3h    { z23.h, z24.h, z25.h }, p3/z, [x13, #-24, mul vl]
+// CHECK-INST: ld3h    { z23.h, z24.h, z25.h }, p3/z, [x13, #-24, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0xc8,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed c8 a4 <unknown>
+
+ld3h    { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl]
+// CHECK-INST: ld3h    { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0xc5,0xa4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 c5 a4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld3w-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld3w-diagnostics.s
new file mode 100644
index 00000000000..6bca3761d45
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld3w-diagnostics.s
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Immediate out of lower bound [-24, 21].
+
+ld3w {z12.s, z13.s, z14.s}, p4/z, [x12, #-27, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3w {z12.s, z13.s, z14.s}, p4/z, [x12, #-27, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3w {z7.s, z8.s, z9.s}, p3/z, [x1, #24, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3w {z7.s, z8.s, z9.s}, p3/z, [x1, #24, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Immediate not a multiple of three.
+
+ld3w {z12.s, z13.s, z14.s}, p4/z, [x12, #-7, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3w {z12.s, z13.s, z14.s}, p4/z, [x12, #-7, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3w {z7.s, z8.s, z9.s}, p3/z, [x1, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21].
+// CHECK-NEXT: ld3w {z7.s, z8.s, z9.s}, p3/z, [x1, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// error: restricted predicate has range [0, 7].
+
+ld3w {z2.s, z3.s, z4.s}, p8/z, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: ld3w {z2.s, z3.s, z4.s}, p8/z, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+ld3w { }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: ld3w { }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld3w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3w { z0.s, z1.s, z2.d }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: ld3w { z0.s, z1.s, z2.d }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3w { z0.s, z1.s, z3.s }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: ld3w { z0.s, z1.s, z3.s }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld3w { v0.4s, v1.4s, v2.4s }, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: ld3w { v0.4s, v1.4s, v2.4s }, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld3w.s b/llvm/test/MC/AArch64/SVE/ld3w.s
new file mode 100644
index 00000000000..9b3cc0a07b0
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/ld3w.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ld3w    { z0.s, z1.s, z2.s }, p0/z, [x0]
+// CHECK-INST: ld3w    { z0.s, z1.s, z2.s }, p0/z, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x40,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 40 a5 <unknown>
+
+ld3w    { z23.s, z24.s, z25.s }, p3/z, [x13, #-24, mul vl]
+// CHECK-INST: ld3w    { z23.s, z24.s, z25.s }, p3/z, [x13, #-24, mul vl]
+// CHECK-ENCODING: [0xb7,0xed,0x48,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 ed 48 a5 <unknown>
+
+ld3w    { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl]
+// CHECK-INST: ld3w    { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl]
+// CHECK-ENCODING: [0x55,0xf5,0x45,0xa5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 55 f5 45 a5 <unknown>