[RISCV] implement li pseudo instruction

The implementation follows the MIPS backend and expands the
pseudo instruction directly during asm parsing. As the result, only
real MC instructions are emitted to the MCStreamer. Additionally,
PseudoLI instructions are emitted during codegen. The actual
expansion to real instructions is performed during MI to MC lowering
and is similar to the expansion performed by the GNU Assembler.

Differential Revision: https://reviews.llvm.org/D41949
Patch by Mario Werner.

llvm-svn: 330224

9 files changed, 270 insertions, 134 deletions

diff --git a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
index 1fbc429cae4..07d60128414 100644
--- a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
@@ -15,10 +15,9 @@ declare i32 @llvm.ctpop.i32(i32)
 define i16 @test_bswap_i16(i16 %a) nounwind {
 ; RV32I-LABEL: test_bswap_i16:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 4080
-; RV32I-NEXT:    mv a1, a1
-; RV32I-NEXT:    slli a2, a0, 8
-; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    slli a1, a0, 8
+; RV32I-NEXT:    lui a2, 4080
+; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    srli a0, a0, 16
@@ -30,16 +29,15 @@ define i16 @test_bswap_i16(i16 %a) nounwind {
 define i32 @test_bswap_i32(i32 %a) nounwind {
 ; RV32I-LABEL: test_bswap_i32:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a1, 16
-; RV32I-NEXT:    addi a1, a1, -256
-; RV32I-NEXT:    srli a2, a0, 8
-; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    srli a1, a0, 8
+; RV32I-NEXT:    lui a2, 16
+; RV32I-NEXT:    addi a2, a2, -256
+; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    srli a2, a0, 24
 ; RV32I-NEXT:    or a1, a1, a2
-; RV32I-NEXT:    lui a2, 4080
-; RV32I-NEXT:    mv a2, a2
-; RV32I-NEXT:    slli a3, a0, 8
-; RV32I-NEXT:    and a2, a3, a2
+; RV32I-NEXT:    slli a2, a0, 8
+; RV32I-NEXT:    lui a3, 4080
+; RV32I-NEXT:    and a2, a2, a3
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    or a0, a0, a2
 ; RV32I-NEXT:    or a0, a0, a1
@@ -51,25 +49,24 @@ define i32 @test_bswap_i32(i32 %a) nounwind {
 define i64 @test_bswap_i64(i64 %a) nounwind {
 ; RV32I-LABEL: test_bswap_i64:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a2, 16
-; RV32I-NEXT:    addi a3, a2, -256
 ; RV32I-NEXT:    srli a2, a1, 8
+; RV32I-NEXT:    lui a3, 16
+; RV32I-NEXT:    addi a3, a3, -256
 ; RV32I-NEXT:    and a2, a2, a3
 ; RV32I-NEXT:    srli a4, a1, 24
 ; RV32I-NEXT:    or a2, a2, a4
-; RV32I-NEXT:    lui a4, 4080
-; RV32I-NEXT:    mv a4, a4
-; RV32I-NEXT:    slli a5, a1, 8
-; RV32I-NEXT:    and a5, a5, a4
+; RV32I-NEXT:    slli a4, a1, 8
+; RV32I-NEXT:    lui a5, 4080
+; RV32I-NEXT:    and a4, a4, a5
 ; RV32I-NEXT:    slli a1, a1, 24
-; RV32I-NEXT:    or a1, a1, a5
+; RV32I-NEXT:    or a1, a1, a4
 ; RV32I-NEXT:    or a2, a1, a2
 ; RV32I-NEXT:    srli a1, a0, 8
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    srli a3, a0, 24
 ; RV32I-NEXT:    or a1, a1, a3
 ; RV32I-NEXT:    slli a3, a0, 8
-; RV32I-NEXT:    and a3, a3, a4
+; RV32I-NEXT:    and a3, a3, a5
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:    or a1, a0, a1
@@ -90,10 +87,10 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
 ; RV32I-NEXT:    addi a1, a0, -1
 ; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    lui a1, 349525
-; RV32I-NEXT:    addi a1, a1, 1365
-; RV32I-NEXT:    srli a2, a0, 1
-; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    srli a1, a0, 1
+; RV32I-NEXT:    lui a2, 349525
+; RV32I-NEXT:    addi a2, a2, 1365
+; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    lui a1, 209715
 ; RV32I-NEXT:    addi a1, a1, 819
@@ -106,10 +103,10 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    lui a1, %hi(__mulsi3)
+; RV32I-NEXT:    addi a2, a1, %lo(__mulsi3)
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
 ; RV32I-NEXT:    jalr a2
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    j .LBB3_3
@@ -136,10 +133,10 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
 ; RV32I-NEXT:    addi a1, a0, -1
 ; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    lui a1, 349525
-; RV32I-NEXT:    addi a1, a1, 1365
-; RV32I-NEXT:    srli a2, a0, 1
-; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    srli a1, a0, 1
+; RV32I-NEXT:    lui a2, 349525
+; RV32I-NEXT:    addi a2, a2, 1365
+; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    lui a1, 209715
 ; RV32I-NEXT:    addi a1, a1, 819
@@ -152,10 +149,10 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    lui a1, %hi(__mulsi3)
+; RV32I-NEXT:    addi a2, a1, %lo(__mulsi3)
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
 ; RV32I-NEXT:    jalr a2
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    j .LBB4_3
@@ -179,10 +176,10 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
 ; RV32I-NEXT:    addi a1, a0, -1
 ; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    lui a1, 349525
-; RV32I-NEXT:    addi a1, a1, 1365
-; RV32I-NEXT:    srli a2, a0, 1
-; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    srli a1, a0, 1
+; RV32I-NEXT:    lui a2, 349525
+; RV32I-NEXT:    addi a2, a2, 1365
+; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    lui a1, 209715
 ; RV32I-NEXT:    addi a1, a1, 819
@@ -195,10 +192,10 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    lui a1, %hi(__mulsi3)
+; RV32I-NEXT:    addi a2, a1, %lo(__mulsi3)
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
 ; RV32I-NEXT:    jalr a2
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    j .LBB5_3
@@ -229,9 +226,9 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    srli a1, a0, 16
 ; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    lui a1, 349525
 ; RV32I-NEXT:    addi a1, a1, 1365
-; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    srli a2, a0, 1
 ; RV32I-NEXT:    and a1, a2, a1
 ; RV32I-NEXT:    sub a0, a0, a1
@@ -246,10 +243,10 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    lui a1, %hi(__mulsi3)
+; RV32I-NEXT:    addi a2, a1, %lo(__mulsi3)
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
 ; RV32I-NEXT:    jalr a2
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    j .LBB6_3
@@ -281,26 +278,26 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    not a1, s3
 ; RV32I-NEXT:    and a0, a1, a0
-; RV32I-NEXT:    lui a1, 349525
-; RV32I-NEXT:    addi s5, a1, 1365
 ; RV32I-NEXT:    srli a1, a0, 1
+; RV32I-NEXT:    lui s5, 349525
+; RV32I-NEXT:    addi s5, s5, 1365
 ; RV32I-NEXT:    and a1, a1, s5
 ; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    lui a1, 209715
-; RV32I-NEXT:    addi s6, a1, 819
+; RV32I-NEXT:    lui s6, 209715
+; RV32I-NEXT:    addi s6, s6, 819
 ; RV32I-NEXT:    and a1, a0, s6
 ; RV32I-NEXT:    srli a0, a0, 2
 ; RV32I-NEXT:    and a0, a0, s6
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    lui a1, 4112
-; RV32I-NEXT:    addi s4, a1, 257
 ; RV32I-NEXT:    lui a1, %hi(__mulsi3)
 ; RV32I-NEXT:    addi s7, a1, %lo(__mulsi3)
-; RV32I-NEXT:    lui a1, 61681
-; RV32I-NEXT:    addi s8, a1, -241
+; RV32I-NEXT:    lui s8, 61681
+; RV32I-NEXT:    addi s8, s8, -241
 ; RV32I-NEXT:    and a0, a0, s8
+; RV32I-NEXT:    lui s4, 4112
+; RV32I-NEXT:    addi s4, s4, 257
 ; RV32I-NEXT:    mv a1, s4
 ; RV32I-NEXT:    jalr s7
 ; RV32I-NEXT:    mv s1, a0
@@ -351,10 +348,10 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
 ; RV32I-NEXT:    addi a1, a0, -1
 ; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    lui a1, 349525
-; RV32I-NEXT:    addi a1, a1, 1365
-; RV32I-NEXT:    srli a2, a0, 1
-; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    srli a1, a0, 1
+; RV32I-NEXT:    lui a2, 349525
+; RV32I-NEXT:    addi a2, a2, 1365
+; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    lui a1, 209715
 ; RV32I-NEXT:    addi a1, a1, 819
@@ -367,10 +364,10 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    lui a1, %hi(__mulsi3)
+; RV32I-NEXT:    addi a2, a1, %lo(__mulsi3)
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
 ; RV32I-NEXT:    jalr a2
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    lw ra, 12(sp)
@@ -388,10 +385,10 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
 ; RV32I-NEXT:    addi a1, a0, -1
 ; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    lui a1, 349525
-; RV32I-NEXT:    addi a1, a1, 1365
-; RV32I-NEXT:    srli a2, a0, 1
-; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    srli a1, a0, 1
+; RV32I-NEXT:    lui a2, 349525
+; RV32I-NEXT:    addi a2, a2, 1365
+; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    lui a1, 209715
 ; RV32I-NEXT:    addi a1, a1, 819
@@ -404,10 +401,10 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    lui a1, %hi(__mulsi3)
+; RV32I-NEXT:    addi a2, a1, %lo(__mulsi3)
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
 ; RV32I-NEXT:    jalr a2
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    lw ra, 12(sp)
@@ -425,10 +422,10 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
 ; RV32I-NEXT:    addi a1, a0, -1
 ; RV32I-NEXT:    not a0, a0
 ; RV32I-NEXT:    and a0, a0, a1
-; RV32I-NEXT:    lui a1, 349525
-; RV32I-NEXT:    addi a1, a1, 1365
-; RV32I-NEXT:    srli a2, a0, 1
-; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    srli a1, a0, 1
+; RV32I-NEXT:    lui a2, 349525
+; RV32I-NEXT:    addi a2, a2, 1365
+; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    lui a1, 209715
 ; RV32I-NEXT:    addi a1, a1, 819
@@ -441,10 +438,10 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    lui a1, %hi(__mulsi3)
+; RV32I-NEXT:    addi a2, a1, %lo(__mulsi3)
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
 ; RV32I-NEXT:    jalr a2
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    lw ra, 12(sp)
@@ -472,26 +469,26 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    not a1, s3
 ; RV32I-NEXT:    and a0, a1, a0
-; RV32I-NEXT:    lui a1, 349525
-; RV32I-NEXT:    addi s5, a1, 1365
 ; RV32I-NEXT:    srli a1, a0, 1
+; RV32I-NEXT:    lui s5, 349525
+; RV32I-NEXT:    addi s5, s5, 1365
 ; RV32I-NEXT:    and a1, a1, s5
 ; RV32I-NEXT:    sub a0, a0, a1
-; RV32I-NEXT:    lui a1, 209715
-; RV32I-NEXT:    addi s6, a1, 819
+; RV32I-NEXT:    lui s6, 209715
+; RV32I-NEXT:    addi s6, s6, 819
 ; RV32I-NEXT:    and a1, a0, s6
 ; RV32I-NEXT:    srli a0, a0, 2
 ; RV32I-NEXT:    and a0, a0, s6
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    add a0, a0, a1
-; RV32I-NEXT:    lui a1, 4112
-; RV32I-NEXT:    addi s4, a1, 257
 ; RV32I-NEXT:    lui a1, %hi(__mulsi3)
 ; RV32I-NEXT:    addi s7, a1, %lo(__mulsi3)
-; RV32I-NEXT:    lui a1, 61681
-; RV32I-NEXT:    addi s8, a1, -241
+; RV32I-NEXT:    lui s8, 61681
+; RV32I-NEXT:    addi s8, s8, -241
 ; RV32I-NEXT:    and a0, a0, s8
+; RV32I-NEXT:    lui s4, 4112
+; RV32I-NEXT:    addi s4, s4, 257
 ; RV32I-NEXT:    mv a1, s4
 ; RV32I-NEXT:    jalr s7
 ; RV32I-NEXT:    mv s1, a0
@@ -539,10 +536,10 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
-; RV32I-NEXT:    lui a1, 349525
-; RV32I-NEXT:    addi a1, a1, 1365
-; RV32I-NEXT:    srli a2, a0, 1
-; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    srli a1, a0, 1
+; RV32I-NEXT:    lui a2, 349525
+; RV32I-NEXT:    addi a2, a2, 1365
+; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    lui a1, 209715
 ; RV32I-NEXT:    addi a1, a1, 819
@@ -555,10 +552,10 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
 ; RV32I-NEXT:    lui a1, 61681
 ; RV32I-NEXT:    addi a1, a1, -241
 ; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    lui a1, %hi(__mulsi3)
+; RV32I-NEXT:    addi a2, a1, %lo(__mulsi3)
 ; RV32I-NEXT:    lui a1, 4112
 ; RV32I-NEXT:    addi a1, a1, 257
-; RV32I-NEXT:    lui a2, %hi(__mulsi3)
-; RV32I-NEXT:    addi a2, a2, %lo(__mulsi3)
 ; RV32I-NEXT:    jalr a2
 ; RV32I-NEXT:    srli a0, a0, 24
 ; RV32I-NEXT:    lw ra, 12(sp)
diff --git a/llvm/test/CodeGen/RISCV/calling-conv.ll b/llvm/test/CodeGen/RISCV/calling-conv.ll
index 8d752cbb6e7..12270ff51b4 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv.ll
@@ -85,14 +85,13 @@ define i32 @caller_scalars() nounwind {
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
-; RV32I-FPELIM-NEXT:    lui a0, 262464
-; RV32I-FPELIM-NEXT:    mv a6, a0
 ; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_scalars)
 ; RV32I-FPELIM-NEXT:    addi a7, a0, %lo(callee_scalars)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    addi a1, zero, 2
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 3
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 4
+; RV32I-FPELIM-NEXT:    lui a6, 262464
 ; RV32I-FPELIM-NEXT:    mv a2, zero
 ; RV32I-FPELIM-NEXT:    mv a5, zero
 ; RV32I-FPELIM-NEXT:    jalr a7
@@ -106,14 +105,13 @@ define i32 @caller_scalars() nounwind {
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
-; RV32I-WITHFP-NEXT:    lui a0, 262464
-; RV32I-WITHFP-NEXT:    mv a6, a0
 ; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_scalars)
 ; RV32I-WITHFP-NEXT:    addi a7, a0, %lo(callee_scalars)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    addi a1, zero, 2
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 3
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 4
+; RV32I-WITHFP-NEXT:    lui a6, 262464
 ; RV32I-WITHFP-NEXT:    mv a2, zero
 ; RV32I-WITHFP-NEXT:    mv a5, zero
 ; RV32I-WITHFP-NEXT:    jalr a7
@@ -187,6 +185,8 @@ define i32 @caller_large_scalars() nounwind {
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -48
 ; RV32I-FPELIM-NEXT:    sw ra, 44(sp)
+; RV32I-FPELIM-NEXT:    lui a0, 524272
+; RV32I-FPELIM-NEXT:    sw a0, 12(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 8(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 4(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 0(sp)
@@ -195,9 +195,6 @@ define i32 @caller_large_scalars() nounwind {
 ; RV32I-FPELIM-NEXT:    sw zero, 28(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
 ; RV32I-FPELIM-NEXT:    sw a0, 24(sp)
-; RV32I-FPELIM-NEXT:    lui a0, 524272
-; RV32I-FPELIM-NEXT:    mv a0, a0
-; RV32I-FPELIM-NEXT:    sw a0, 12(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_large_scalars)
 ; RV32I-FPELIM-NEXT:    addi a2, a0, %lo(callee_large_scalars)
 ; RV32I-FPELIM-NEXT:    addi a0, sp, 24
@@ -213,6 +210,8 @@ define i32 @caller_large_scalars() nounwind {
 ; RV32I-WITHFP-NEXT:    sw ra, 44(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 40(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 48
+; RV32I-WITHFP-NEXT:    lui a0, 524272
+; RV32I-WITHFP-NEXT:    sw a0, -36(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -40(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -44(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -48(s0)
@@ -221,9 +220,6 @@ define i32 @caller_large_scalars() nounwind {
 ; RV32I-WITHFP-NEXT:    sw zero, -20(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
 ; RV32I-WITHFP-NEXT:    sw a0, -24(s0)
-; RV32I-WITHFP-NEXT:    lui a0, 524272
-; RV32I-WITHFP-NEXT:    mv a0, a0
-; RV32I-WITHFP-NEXT:    sw a0, -36(s0)
 ; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_large_scalars)
 ; RV32I-WITHFP-NEXT:    addi a2, a0, %lo(callee_large_scalars)
 ; RV32I-WITHFP-NEXT:    addi a0, s0, -24
@@ -306,6 +302,8 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
 ; RV32I-FPELIM-NEXT:    sw a0, 4(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 9
 ; RV32I-FPELIM-NEXT:    sw a0, 0(sp)
+; RV32I-FPELIM-NEXT:    lui a0, 524272
+; RV32I-FPELIM-NEXT:    sw a0, 28(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 24(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 20(sp)
 ; RV32I-FPELIM-NEXT:    sw zero, 16(sp)
@@ -314,9 +312,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
 ; RV32I-FPELIM-NEXT:    sw zero, 44(sp)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 8
 ; RV32I-FPELIM-NEXT:    sw a0, 40(sp)
-; RV32I-FPELIM-NEXT:    lui a0, 524272
-; RV32I-FPELIM-NEXT:    mv a0, a0
-; RV32I-FPELIM-NEXT:    sw a0, 28(sp)
 ; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_large_scalars_exhausted_regs)
 ; RV32I-FPELIM-NEXT:    addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
@@ -342,6 +337,8 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
 ; RV32I-WITHFP-NEXT:    sw a0, 4(sp)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 9
 ; RV32I-WITHFP-NEXT:    sw a0, 0(sp)
+; RV32I-WITHFP-NEXT:    lui a0, 524272
+; RV32I-WITHFP-NEXT:    sw a0, -36(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -40(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -44(s0)
 ; RV32I-WITHFP-NEXT:    sw zero, -48(s0)
@@ -350,9 +347,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
 ; RV32I-WITHFP-NEXT:    sw zero, -20(s0)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 8
 ; RV32I-WITHFP-NEXT:    sw a0, -24(s0)
-; RV32I-WITHFP-NEXT:    lui a0, 524272
-; RV32I-WITHFP-NEXT:    mv a0, a0
-; RV32I-WITHFP-NEXT:    sw a0, -36(s0)
 ; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_large_scalars_exhausted_regs)
 ; RV32I-WITHFP-NEXT:    addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
@@ -776,8 +770,6 @@ define void @caller_aligned_stack() nounwind {
 ; RV32I-FPELIM-NEXT:    lui a0, 335544
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 1311
 ; RV32I-FPELIM-NEXT:    sw a0, 32(sp)
-; RV32I-FPELIM-NEXT:    lui a0, 688509
-; RV32I-FPELIM-NEXT:    addi a5, a0, -2048
 ; RV32I-FPELIM-NEXT:    lui a0, %hi(callee_aligned_stack)
 ; RV32I-FPELIM-NEXT:    addi t0, a0, %lo(callee_aligned_stack)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
@@ -785,6 +777,8 @@ define void @caller_aligned_stack() nounwind {
 ; RV32I-FPELIM-NEXT:    addi a2, sp, 32
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 12
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 13
+; RV32I-FPELIM-NEXT:    lui a5, 688509
+; RV32I-FPELIM-NEXT:    addi a5, a5, -2048
 ; RV32I-FPELIM-NEXT:    addi a6, zero, 4
 ; RV32I-FPELIM-NEXT:    addi a7, zero, 14
 ; RV32I-FPELIM-NEXT:    jalr t0
@@ -824,8 +818,6 @@ define void @caller_aligned_stack() nounwind {
 ; RV32I-WITHFP-NEXT:    lui a0, 335544
 ; RV32I-WITHFP-NEXT:    addi a0, a0, 1311
 ; RV32I-WITHFP-NEXT:    sw a0, -32(s0)
-; RV32I-WITHFP-NEXT:    lui a0, 688509
-; RV32I-WITHFP-NEXT:    addi a5, a0, -2048
 ; RV32I-WITHFP-NEXT:    lui a0, %hi(callee_aligned_stack)
 ; RV32I-WITHFP-NEXT:    addi t0, a0, %lo(callee_aligned_stack)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
@@ -833,6 +825,8 @@ define void @caller_aligned_stack() nounwind {
 ; RV32I-WITHFP-NEXT:    addi a2, s0, -32
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 12
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 13
+; RV32I-WITHFP-NEXT:    lui a5, 688509
+; RV32I-WITHFP-NEXT:    addi a5, a5, -2048
 ; RV32I-WITHFP-NEXT:    addi a6, zero, 4
 ; RV32I-WITHFP-NEXT:    addi a7, zero, 14
 ; RV32I-WITHFP-NEXT:    jalr t0
@@ -987,7 +981,6 @@ define fp128 @callee_large_scalar_ret() nounwind {
 ; RV32I-FPELIM-LABEL: callee_large_scalar_ret:
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    lui a1, 524272
-; RV32I-FPELIM-NEXT:    mv a1, a1
 ; RV32I-FPELIM-NEXT:    sw a1, 12(a0)
 ; RV32I-FPELIM-NEXT:    sw zero, 8(a0)
 ; RV32I-FPELIM-NEXT:    sw zero, 4(a0)
@@ -1001,7 +994,6 @@ define fp128 @callee_large_scalar_ret() nounwind {
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32I-WITHFP-NEXT:    lui a1, 524272
-; RV32I-WITHFP-NEXT:    mv a1, a1
 ; RV32I-WITHFP-NEXT:    sw a1, 12(a0)
 ; RV32I-WITHFP-NEXT:    sw zero, 8(a0)
 ; RV32I-WITHFP-NEXT:    sw zero, 4(a0)
diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll
index c7c5f91301e..f3ec61b4357 100644
--- a/llvm/test/CodeGen/RISCV/float-arith.ll
+++ b/llvm/test/CodeGen/RISCV/float-arith.ll
@@ -84,7 +84,6 @@ define float @fneg_s(float %a) nounwind {
 ; RV32IF-LABEL: fneg_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    lui a1, 524288
-; RV32IF-NEXT:    mv a1, a1
 ; RV32IF-NEXT:    xor a0, a0, a1
 ; RV32IF-NEXT:    ret
   %1 = fsub float -0.0, %a
@@ -97,7 +96,6 @@ define float @fsgnjn_s(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fsgnjn_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    lui a2, 524288
-; RV32IF-NEXT:    mv a2, a2
 ; RV32IF-NEXT:    xor a1, a1, a2
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll
index 61a6178e095..9e7131bbd28 100644
--- a/llvm/test/CodeGen/RISCV/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/vararg.ll
@@ -264,10 +264,9 @@ define void @va1_caller() nounwind {
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
-; RV32I-FPELIM-NEXT:    lui a0, 261888
-; RV32I-FPELIM-NEXT:    mv a3, a0
 ; RV32I-FPELIM-NEXT:    lui a0, %hi(va1)
 ; RV32I-FPELIM-NEXT:    addi a0, a0, %lo(va1)
+; RV32I-FPELIM-NEXT:    lui a3, 261888
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 2
 ; RV32I-FPELIM-NEXT:    mv a2, zero
 ; RV32I-FPELIM-NEXT:    jalr a0
@@ -281,10 +280,9 @@ define void @va1_caller() nounwind {
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
-; RV32I-WITHFP-NEXT:    lui a0, 261888
-; RV32I-WITHFP-NEXT:    mv a3, a0
 ; RV32I-WITHFP-NEXT:    lui a0, %hi(va1)
 ; RV32I-WITHFP-NEXT:    addi a0, a0, %lo(va1)
+; RV32I-WITHFP-NEXT:    lui a3, 261888
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 2
 ; RV32I-WITHFP-NEXT:    mv a2, zero
 ; RV32I-WITHFP-NEXT:    jalr a0
@@ -472,10 +470,9 @@ define void @va2_caller() nounwind {
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
-; RV32I-FPELIM-NEXT:    lui a0, 261888
-; RV32I-FPELIM-NEXT:    mv a3, a0
 ; RV32I-FPELIM-NEXT:    lui a0, %hi(va2)
 ; RV32I-FPELIM-NEXT:    addi a0, a0, %lo(va2)
+; RV32I-FPELIM-NEXT:    lui a3, 261888
 ; RV32I-FPELIM-NEXT:    mv a2, zero
 ; RV32I-FPELIM-NEXT:    jalr a0
 ; RV32I-FPELIM-NEXT:    lw ra, 12(sp)
@@ -488,10 +485,9 @@ define void @va2_caller() nounwind {
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
-; RV32I-WITHFP-NEXT:    lui a0, 261888
-; RV32I-WITHFP-NEXT:    mv a3, a0
 ; RV32I-WITHFP-NEXT:    lui a0, %hi(va2)
 ; RV32I-WITHFP-NEXT:    addi a0, a0, %lo(va2)
+; RV32I-WITHFP-NEXT:    lui a3, 261888
 ; RV32I-WITHFP-NEXT:    mv a2, zero
 ; RV32I-WITHFP-NEXT:    jalr a0
 ; RV32I-WITHFP-NEXT:    lw s0, 8(sp)
@@ -716,13 +712,11 @@ define void @va3_caller() nounwind {
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -16
 ; RV32I-FPELIM-NEXT:    sw ra, 12(sp)
-; RV32I-FPELIM-NEXT:    lui a0, 261888
-; RV32I-FPELIM-NEXT:    mv a2, a0
-; RV32I-FPELIM-NEXT:    lui a0, 262144
-; RV32I-FPELIM-NEXT:    mv a5, a0
 ; RV32I-FPELIM-NEXT:    lui a0, %hi(va3)
 ; RV32I-FPELIM-NEXT:    addi a3, a0, %lo(va3)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 2
+; RV32I-FPELIM-NEXT:    lui a2, 261888
+; RV32I-FPELIM-NEXT:    lui a5, 262144
 ; RV32I-FPELIM-NEXT:    mv a1, zero
 ; RV32I-FPELIM-NEXT:    mv a4, zero
 ; RV32I-FPELIM-NEXT:    jalr a3
@@ -736,13 +730,11 @@ define void @va3_caller() nounwind {
 ; RV32I-WITHFP-NEXT:    sw ra, 12(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 8(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 16
-; RV32I-WITHFP-NEXT:    lui a0, 261888
-; RV32I-WITHFP-NEXT:    mv a2, a0
-; RV32I-WITHFP-NEXT:    lui a0, 262144
-; RV32I-WITHFP-NEXT:    mv a5, a0
 ; RV32I-WITHFP-NEXT:    lui a0, %hi(va3)
 ; RV32I-WITHFP-NEXT:    addi a3, a0, %lo(va3)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 2
+; RV32I-WITHFP-NEXT:    lui a2, 261888
+; RV32I-WITHFP-NEXT:    lui a5, 262144
 ; RV32I-WITHFP-NEXT:    mv a1, zero
 ; RV32I-WITHFP-NEXT:    mv a4, zero
 ; RV32I-WITHFP-NEXT:    jalr a3
@@ -1035,8 +1027,6 @@ define void @va5_aligned_stack_caller() nounwind {
 ; RV32I-FPELIM-NEXT:    lui a0, 335544
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 1311
 ; RV32I-FPELIM-NEXT:    sw a0, 32(sp)
-; RV32I-FPELIM-NEXT:    lui a0, 688509
-; RV32I-FPELIM-NEXT:    addi a6, a0, -2048
 ; RV32I-FPELIM-NEXT:    lui a0, %hi(va5_aligned_stack_callee)
 ; RV32I-FPELIM-NEXT:    addi a5, a0, %lo(va5_aligned_stack_callee)
 ; RV32I-FPELIM-NEXT:    addi a0, zero, 1
@@ -1044,6 +1034,8 @@ define void @va5_aligned_stack_caller() nounwind {
 ; RV32I-FPELIM-NEXT:    addi a2, sp, 32
 ; RV32I-FPELIM-NEXT:    addi a3, zero, 12
 ; RV32I-FPELIM-NEXT:    addi a4, zero, 13
+; RV32I-FPELIM-NEXT:    lui a6, 688509
+; RV32I-FPELIM-NEXT:    addi a6, a6, -2048
 ; RV32I-FPELIM-NEXT:    addi a7, zero, 4
 ; RV32I-FPELIM-NEXT:    jalr a5
 ; RV32I-FPELIM-NEXT:    lw ra, 60(sp)
@@ -1082,8 +1074,6 @@ define void @va5_aligned_stack_caller() nounwind {
 ; RV32I-WITHFP-NEXT:    lui a0, 335544
 ; RV32I-WITHFP-NEXT:    addi a0, a0, 1311
 ; RV32I-WITHFP-NEXT:    sw a0, -32(s0)
-; RV32I-WITHFP-NEXT:    lui a0, 688509
-; RV32I-WITHFP-NEXT:    addi a6, a0, -2048
 ; RV32I-WITHFP-NEXT:    lui a0, %hi(va5_aligned_stack_callee)
 ; RV32I-WITHFP-NEXT:    addi a5, a0, %lo(va5_aligned_stack_callee)
 ; RV32I-WITHFP-NEXT:    addi a0, zero, 1
@@ -1091,6 +1081,8 @@ define void @va5_aligned_stack_caller() nounwind {
 ; RV32I-WITHFP-NEXT:    addi a2, s0, -32
 ; RV32I-WITHFP-NEXT:    addi a3, zero, 12
 ; RV32I-WITHFP-NEXT:    addi a4, zero, 13
+; RV32I-WITHFP-NEXT:    lui a6, 688509
+; RV32I-WITHFP-NEXT:    addi a6, a6, -2048
 ; RV32I-WITHFP-NEXT:    addi a7, zero, 4
 ; RV32I-WITHFP-NEXT:    jalr a5
 ; RV32I-WITHFP-NEXT:    lw s0, 56(sp)
diff --git a/llvm/test/MC/RISCV/rv32i-aliases-invalid.s b/llvm/test/MC/RISCV/rv32i-aliases-invalid.s
index e0473ca371d..37cd36c3b40 100644
--- a/llvm/test/MC/RISCV/rv32i-aliases-invalid.s
+++ b/llvm/test/MC/RISCV/rv32i-aliases-invalid.s
@@ -4,5 +4,12 @@
 # TODO ld
 # TODO sd
 
+li x0, 4294967296   # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
+li x0, -2147483649  # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
+li t4, foo          # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
+
 negw x1, x2   # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
 sext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
+
+foo:
+  .space 4
diff --git a/llvm/test/MC/RISCV/rv32i-aliases-valid.s b/llvm/test/MC/RISCV/rv32i-aliases-valid.s
index f4f35c543ac..84ed1ec3c30 100644
--- a/llvm/test/MC/RISCV/rv32i-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv32i-aliases-valid.s
@@ -1,13 +1,71 @@
 # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases \
-# RUN:     | FileCheck -check-prefixes=CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
 # RUN: llvm-mc %s -triple=riscv32 \
-# RUN:     | FileCheck -check-prefixes=CHECK-ALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-objdump -riscv-no-aliases -d - \
-# RUN:     | FileCheck -check-prefixes=CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-objdump -d - \
-# RUN:     | FileCheck -check-prefixes=CHECK-ALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
+
+# The following check prefixes are used in this test:
+# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
+# CHECK-ALIAS....Match the alias (tests instr. to alias mapping)
+# CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion)
+
+# CHECK-INST: addi a0, zero, 0
+# CHECK-ALIAS: mv a0, zero
+li x10, 0
+# CHECK-EXPAND: addi a0, zero, 1
+li x10, 1
+# CHECK-EXPAND: addi a0, zero, -1
+li x10, -1
+# CHECK-EXPAND: addi a0, zero, 2047
+li x10, 2047
+# CHECK-EXPAND: addi a0, zero, -2047
+li x10, -2047
+# CHECK-EXPAND: lui a1, 1
+# CHECK-EXPAND: addi a1, a1, -2048
+li x11, 2048
+# CHECK-EXPAND: addi a1, zero, -2048
+li x11, -2048
+# CHECK-EXPAND: lui a1, 1
+# CHECK-EXPAND: addi a1, a1, -2047
+li x11, 2049
+# CHECK-EXPAND: lui a1, 1048575
+# CHECK-EXPAND: addi a1, a1, 2047
+li x11, -2049
+# CHECK-EXPAND: lui a1, 1
+# CHECK-EXPAND: addi a1, a1, -1
+li x11, 4095
+# CHECK-EXPAND: lui a1, 1048575
+# CHECK-EXPAND: addi a1, a1, 1
+li x11, -4095
+# CHECK-EXPAND: lui a2, 1
+li x12, 4096
+# CHECK-EXPAND: lui a2, 1048575
+li x12, -4096
+# CHECK-EXPAND: lui a2, 1
+# CHECK-EXPAND: addi a2, a2, 1
+li x12, 4097
+# CHECK-EXPAND: lui a2, 1048575
+# CHECK-EXPAND: addi a2, a2, -1
+li x12, -4097
+# CHECK-EXPAND: lui a2, 524288
+# CHECK-EXPAND: addi a2, a2, -1
+li x12, 2147483647
+# CHECK-EXPAND: lui a2, 524288
+# CHECK-EXPAND: addi a2, a2, 1
+li x12, -2147483647
+# CHECK-EXPAND: lui a2, 524288
+li x12, -2147483648
+# CHECK-EXPAND: lui a2, 524288
+li x12, 0x80000000
+# CHECK-EXPAND: lui a2, 524288
+li x12, -0x80000000
+# CHECK-EXPAND: addi a2, zero, -1
+li x12, 0xFFFFFFFF
 
 # CHECK-INST: csrrs t4, 3202, zero
 # CHECK-ALIAS: rdinstreth t4
diff --git a/llvm/test/MC/RISCV/rv64i-aliases-invalid.s b/llvm/test/MC/RISCV/rv64i-aliases-invalid.s
index f8e3991f1c9..e21601b51a4 100644
--- a/llvm/test/MC/RISCV/rv64i-aliases-invalid.s
+++ b/llvm/test/MC/RISCV/rv64i-aliases-invalid.s
@@ -1,6 +1,12 @@
 # RUN: not llvm-mc %s -triple=riscv64 -riscv-no-aliases 2>&1 | FileCheck %s
 # RUN: not llvm-mc %s -triple=riscv64 2>&1 | FileCheck %s
 
+li t5, 0x10000000000000000 # CHECK: :[[@LINE]]:8: error: unknown operand
+li t4, foo                 # CHECK: :[[@LINE]]:8: error: operand must be a constant 64-bit integer
+
 rdinstreth x29 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
 rdcycleh x27   # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
 rdtimeh x28    # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
+
+foo:
+  .space 8
diff --git a/llvm/test/MC/RISCV/rv64i-aliases-valid.s b/llvm/test/MC/RISCV/rv64i-aliases-valid.s
index 953493e147b..edfa66e0463 100644
--- a/llvm/test/MC/RISCV/rv64i-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv64i-aliases-valid.s
@@ -1,17 +1,100 @@
 # RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases \
-# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
 # RUN: llvm-mc %s -triple=riscv64 \
-# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:     | llvm-objdump -riscv-no-aliases -d - \
-# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:     | llvm-objdump -d - \
-# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
+
+# The following check prefixes are used in this test:
+# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
+# CHECK-ALIAS....Match the alias (tests instr. to alias mapping)
+# CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion)
 
 # TODO ld
 # TODO sd
 
+# CHECK-INST: addiw a0, zero, 0
+# CHECK-ALIAS: sext.w a0, zero
+li x10, 0
+# CHECK-EXPAND: addiw a0, zero, 1
+li x10, 1
+# CHECK-EXPAND: addiw a0, zero, -1
+li x10, -1
+# CHECK-EXPAND: addiw a0, zero, 2047
+li x10, 2047
+# CHECK-EXPAND: addiw a0, zero, -2047
+li x10, -2047
+# CHECK-EXPAND: lui a1, 1
+# CHECK-EXPAND: addiw a1, a1, -2048
+li x11, 2048
+# CHECK-EXPAND: addiw a1, zero, -2048
+li x11, -2048
+# CHECK-EXPAND: lui a1, 1
+# CHECK-EXPAND: addiw a1, a1, -2047
+li x11, 2049
+# CHECK-EXPAND: lui a1, 1048575
+# CHECK-EXPAND: addiw a1, a1, 2047
+li x11, -2049
+# CHECK-EXPAND: lui a1, 1
+# CHECK-EXPAND: addiw a1, a1, -1
+li x11, 4095
+# CHECK-EXPAND: lui a1, 1048575
+# CHECK-EXPAND: addiw a1, a1, 1
+li x11, -4095
+# CHECK-EXPAND: lui a2, 1
+li x12, 4096
+# CHECK-EXPAND: lui a2, 1048575
+li x12, -4096
+# CHECK-EXPAND: lui a2, 1
+# CHECK-EXPAND: addiw a2, a2, 1
+li x12, 4097
+# CHECK-EXPAND: lui a2, 1048575
+# CHECK-EXPAND: addiw a2, a2, -1
+li x12, -4097
+# CHECK-EXPAND: lui a2, 524288
+# CHECK-EXPAND: addiw a2, a2, -1
+li x12, 2147483647
+# CHECK-EXPAND: lui a2, 524288
+# CHECK-EXPAND: addiw a2, a2, 1
+li x12, -2147483647
+# CHECK-EXPAND: lui a2, 524288
+li x12, -2147483648
+
+# CHECK-EXPAND: addiw t0, zero, 1
+# CHECK-EXPAND: slli t0, t0, 32
+li t0, 0x100000000
+# CHECK-EXPAND: addiw t1, zero, -1
+# CHECK-EXPAND: slli t1, t1, 63
+li t1, 0x8000000000000000
+# CHECK-EXPAND: addiw t1, zero, -1
+# CHECK-EXPAND: slli t1, t1, 63
+li t1, -0x8000000000000000
+# CHECK-EXPAND: lui t2, 9321
+# CHECK-EXPAND: addiw t2, t2, -1329
+# CHECK-EXPAND: slli t2, t2, 35
+li t2, 0x1234567800000000
+# CHECK-EXPAND: addiw t3, zero, 7
+# CHECK-EXPAND: slli t3, t3, 36
+# CHECK-EXPAND: addi t3, t3, 11
+# CHECK-EXPAND: slli t3, t3, 24
+# CHECK-EXPAND: addi t3, t3, 15
+li t3, 0x700000000B00000F
+# CHECK-EXPAND: lui t4, 583
+# CHECK-EXPAND: addiw t4, t4, -1875
+# CHECK-EXPAND: slli t4, t4, 14
+# CHECK-EXPAND: addi t4, t4, -947
+# CHECK-EXPAND: slli t4, t4, 12
+# CHECK-EXPAND: addi t4, t4, 1511
+# CHECK-EXPAND: slli t4, t4, 13
+# CHECK-EXPAND: addi t4, t4, -272
+li t4, 0x123456789abcdef0
+# CHECK-EXPAND: addiw t5, zero, -1
+li t5, 0xFFFFFFFFFFFFFFFF
+
 # CHECK-INST: subw t6, zero, ra
 # CHECK-ALIAS: negw t6, ra
 negw x31, x1
diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s
index 72ed72eab27..2ad1b3c65d2 100644
--- a/llvm/test/MC/RISCV/rvi-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvi-aliases-valid.s
@@ -19,6 +19,10 @@
 # RUN:     | llvm-objdump -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
 
+# The following check prefixes are used in this test:
+# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
+# CHECK-ALIAS....Match the alias (tests instr. to alias mapping)
+
 # TODO la
 # TODO lb lh lw
 # TODO sb sh sw
@@ -26,7 +30,6 @@
 # CHECK-INST: addi zero, zero, 0
 # CHECK-ALIAS: nop
 nop
-# TODO li
 # CHECK-INST: addi t6, zero, 0
 # CHECK-ALIAS: mv t6, zero
 mv x31, zero