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* Recommit r256952 "Filtering IR printing for print-after-all/print-before-all"Weiming Zhao2016-01-061-1/+13
| | | | | | | | Fix lit test fail due to outputting an extra line. Differential Revision: http://reviews.llvm.org/D15776 llvm-svn: 256987
* Bitcode: Fix reading and writing of ConstantDataVectors of halfsJustin Bogner2016-01-061-0/+32
| | | | | | | | | | | | In r254991 I allowed ConstantDataVectors to contain elements of HalfTy, but I missed updating the bitcode reader and writer to handle this, so now we crash if we try to emit bitcode on programs that have constant vectors of half. This fixes the issue and adds test coverage for reading and writing constant sequences in bitcode. llvm-svn: 256982
* AMDGPU/SI: Fix crash when inline assembly is used in a graphics shaderNicolai Haehnle2016-01-061-0/+11
| | | | | | | | | | | | | | | Summary: This is admittedly something that you could only run into by manually playing around with shader assembly because the SITypeWriter pass is skipped for compute. Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15902 llvm-svn: 256980
* [SplitLandingPadPredecessors] Create a PHINode for the original landingpad ↵Chen Li2016-01-061-0/+33
| | | | | | | | | | | | | | only if it has some uses Summary: This patch adds a check in SplitLandingPadPredecessors to see if the original landingpad instruction has any uses. If not, we don't need to create a PHINode for it in the joint block since it's gonna be a dead code anyway. The motivation for this patch is that we found a bug that SplitLandingPadPredecessors created a PHINode of token type landingpad, which failed the verifier since PHINode can not be token type. However, the created PHINode will never be used in our code pattern. This patch will workaround this bug, and we might add supports in SplitLandingPadPredecessors to handle token type landingpad with uses in the future. Reviewers: reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15835 llvm-svn: 256972
* Promote aggregate store to memset when possibleAmaury Sechet2016-01-061-4/+6
| | | | | | | | | | | | Summary: As per title. This will allow the optimizer to pick up on it. Reviewers: craig.topper, spatel, dexonsmith, Prazek, chandlerc, joker.eph, majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15923 llvm-svn: 256969
* [LibCallSimplifier] use instruction-level fast-math-flags for tan/atan transformSanjay Patel2016-01-061-10/+9
| | | | llvm-svn: 256964
* [X86] Correctly model TLS calls w.r.t. frame requirements.Quentin Colombet2016-01-062-1/+49
| | | | | | | | | TLS calls need the stack frame to be properly set up and this implies that such calls need ADJUSTSTACK_xxx markers. Fixes PR25820. llvm-svn: 256959
* Make WinCOFFObjectWriter.cpp's timestamp writing not use ENABLE_TIMESTAMPSNico Weber2016-01-063-6/+0
| | | | | | | | | | | | | | | | | | | | | LLVM_ENABLE_TIMESTAMPS controls if timestamps are embedded into llvm's binaries. Turning it off is useful for deterministic builds. r246905 made it so that the define suddenly also controls if the binaries that the llvm binaries _create_ embed timestamps or not – but this shouldn't be a configure-time option. r256203/r256204 added a driver option to toggle this on and off, so this patch now passes this driver option in LLVM_ENABLE_TIMESTAMPS builds so that if LLVM_ENABLE_TIMESTAMPS is set, the build of LLVM is deterministic – but the built clang can still write timestamps into other executables when requested. This also allows removing some of the test machinery added in r292012 to work around this problem. See PR24740 for background. http://reviews.llvm.org/D15783 llvm-svn: 256958
* [ShrinkWrap] Fix FindIDom to only have one kind of failure.Michael Kuperstein2016-01-061-0/+32
| | | | | | | | | | | | | FindIDom() can fail in two different ways - it can either return nullptr or the block itself, depending on the circumstances. Some users of FindIDom() check one error condition, while others check the other. Change it to always return nullptr on failure. This fixes PR26004. Differential Revision: http://reviews.llvm.org/D15847 llvm-svn: 256955
* Revert r256952 due to lit test fails.Weiming Zhao2016-01-061-13/+1
| | | | llvm-svn: 256954
* [WebAssembly] Don't use range-based loop for a list that's being modifiedDan Gohman2016-01-061-0/+1
| | | | | | | | The first instruction in a block is what the rend() iterator points to, so if it moves, we need to re-evaluate rend() so that we continue to iterate through the rest of the instructions. llvm-svn: 256953
* Filtering IR printing for print-after-all/print-before-allWeiming Zhao2016-01-061-1/+13
| | | | | | | | | | | | | | | Summary: This patch implements "-print-funcs" option to support function filtering for IR printing like -print-after-all, -print-before etc. Examples: -print-after-all -print-funcs=foo,bar Reviewers: mcrosier, joker.eph Subscribers: tejohnson, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D15776 llvm-svn: 256952
* ScheduleDAGInstrs: Bug fix for missed memory dependency.Geoff Berry2016-01-061-0/+22
| | | | | | | | | | | | | | | | | | | | Summary: In buildSchedGraph(), when adding memory dependencies for loads, move the call to adjustChainDeps() after the call to addChainDependency(AliasChain) to handle the case where addChainDependency(AliasChain) ends up not adding a dependency and instead putting the SU on the RejectMemNodes list. The call to adjustChainDeps() must be done after the call to addChainDependency() in order to process the SU added to the RejectMemNodes list to create memory dependencies for it. Reviewers: hfinkel, atrick, jonpa, resistor Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D15927 llvm-svn: 256950
* [WebAssembly] Add -asm-verbose=false to llc tests.Dan Gohman2016-01-061-8/+8
| | | | | | | In general, disabling comments in the output reduces the chances of a CHECK line accidentally matching a comment instead of its intended text. llvm-svn: 256946
* Revert "GlobalsAA: Take advantage of ArgMemOnly, InaccessibleMemOnly and ↵Amaury Sechet2016-01-063-67/+21
| | | | | | | | | | | | | | | | | | | InaccessibleMemOrArgMemOnly attributes" Summary: This reverts commit 5a9e526f29cf8510ab5c3d566fbdcf47ac24e1e9. As per discussion in D15665 This also add a test case so that regression introduced by that diff are not reintroduced. Reviewers: vaivaswatha, jmolloy, hfinkel, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15919 llvm-svn: 256932
* PR25754: avoid generating UDIVREM8_ZEXT_HREG nodes with i64 resultArtyom Skrobov2016-01-061-0/+19
| | | | | | | | | | Reviewers: spatel, srking Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15331 llvm-svn: 256924
* Improve load/store to memcpy for aggregateAmaury Sechet2016-01-061-0/+25
| | | | | | | | | | | | Summary: It turns out that if we don't try to do it at the store location, we can do it before any operation that alias the load, as long as no operation alias the store. Reviewers: craig.topper, spatel, dexonsmith, Prazek, chandlerc, joker.eph Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15903 llvm-svn: 256923
* [X86][SSE] There is no zmm addsubpd/addsubps instruction.Simon Pilgrim2016-01-061-1/+58
| | | | | | Replace the assert in combineShuffleToAddSub with an early out. llvm-svn: 256922
* [BasicAA] Remove special casing of memset_pattern16 in favor of generic ↵Philip Reames2016-01-062-1/+6
| | | | | | | | | | | | attribute inference Most of the properties of memset_pattern16 can be now covered by the generic attributes and inferred by InferFunctionAttrs. The only exceptions are: - We don't yet have a writeonly attribute for the first argument. - We don't have an attribute for modeling the access size facts encoded in MemoryLocation.cpp. Differential Revision: http://reviews.llvm.org/D15879 llvm-svn: 256911
* [SelectionDAGBuilder] Set NoUnsignedWrap for inbounds gep and load/store ↵Dan Gohman2016-01-061-0/+198
| | | | | | | | | | | | | | | | | | | | offsets. In an inbounds getelementptr, when an index produces a constant non-negative offset to add to the base, the add can be assumed to not have unsigned overflow. This relies on the assumption that addresses can't occupy more than half the address space, which isn't possible in C because it wouldn't be possible to represent the difference between the start of the object and one-past-the-end in a ptrdiff_t. Setting the NoUnsignedWrap flag is theoretically useful in general, and is specifically useful to the WebAssembly backend, since it permits stronger constant offset folding. Differential Revision: http://reviews.llvm.org/D15544 llvm-svn: 256890
* [Statepoints] Check for the "gc-leaf-function" attribute on call sites as well.Manuel Jacob2016-01-051-0/+11
| | | | | | | | | | Reviewers: sanjoy, reames Subscribers: sanjoy, llvm-commits Differential Revision: http://reviews.llvm.org/D15900 llvm-svn: 256875
* [LibCallSimplfier] use instruction-level fast-math-flags for fmin/fmax ↵Sanjay Patel2016-01-051-17/+16
| | | | | | transforms llvm-svn: 256871
* AMDGPU/SI: Do not move scratch resource register on Tonga & IcelandNicolai Haehnle2016-01-053-3/+27
| | | | | | | | | | | | | Due to the SGPR init bug, every program claims to use the same number of SGPRs anyway, so there's no point in trying to shift those registers down from their initial spot of reservation. Add a test that uses VGPR spilling and blocks most SGPRs from being used for the scratch resource register. Previously, this would run into an assertion. Differential Revision: http://reviews.llvm.org/D15724 llvm-svn: 256870
* Implement load to store => memcpy in MemCpyOpt for aggregatesAmaury Sechet2016-01-051-0/+47
| | | | | | | | | | | | | | | Summary: Most of the tool chain is able to optimize scalar and memcpy like operation effisciently while it isn't that good with aggregates. In order to improve the support of aggregate, we try to change aggregate manipulation into either scalar or memcpy like ones whenever possible without loosing informations. This is one such opportunity. Reviewers: craig.topper, spatel, dexonsmith, Prazek, chandlerc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15894 llvm-svn: 256868
* Correct my last commit (revision 256860).Manuel Jacob2016-01-051-2/+2
| | | | | | I forgot to save a small wording improvement before committing. llvm-svn: 256862
* [PlaceSafepoints] Add a test.Manuel Jacob2016-01-051-0/+24
| | | | | | | Calls of functions with the "gc-leaf-function" attribute shouldn't be turned into a safepoint. llvm-svn: 256860
* [InstCombine] insert a new shuffle before its uses (PR26015)Sanjay Patel2016-01-051-0/+53
| | | | | | | | | | | | | | | | Although this solves the test case in PR26015: https://llvm.org/bugs/show_bug.cgi?id=26015 And may solve PR25999: https://llvm.org/bugs/show_bug.cgi?id=25999 ...I suspect this is not the best solution. I think we want to insert the new shuffle just ahead of the earliest ExtractElementInst that we're replacing, but I don't know how that should be implemented. Differential Revision: http://reviews.llvm.org/D15878 llvm-svn: 256857
* [AVX512] add PSLLD and PSLLQ IntrinsicMichael Zuckerman2016-01-052-0/+189
| | | | | | Differential Revision: http://reviews.llvm.org/D15885 llvm-svn: 256840
* [AArch64] Add support for Samsung Exynos-M1MinSeong Kim2016-01-053-0/+38
| | | | | | | | Adds core tuning support for new Samsung Exynos-M1 core (ARMv8-A). Differential Revision: http://reviews.llvm.org/D15663 llvm-svn: 256828
* [SimplifyCFG] Further improve our ability to remove redundant catchpadsDavid Majnemer2016-01-051-0/+66
| | | | | | | | | In r256814, we managed to remove catchpads which were trivially redudant because they were the same SSA value. We can do better using the same algorithm but with a smarter datastructure by hashing the SSA values within the catchpad and comparing them structurally. llvm-svn: 256815
* [SimplifyCFG] Remove redundant catchpadsDavid Majnemer2016-01-051-0/+18
| | | | | | Remove duplicate catchpad handlers from a catchswitch. llvm-svn: 256814
* AMDGPU/SI: Select non-uniform constant addrspace loads to flat instructions ↵Tom Stellard2016-01-052-165/+244
| | | | | | | | | | | | | | for HSA Summary: This fixes a regression caused by r256282. Reviewers: arsenm, cfang Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15736 llvm-svn: 256810
* [WinEH] Simplify unreachable catchpadsJoseph Tremoulet2016-01-051-0/+115
| | | | | | | | | | | | | | | | Summary: At least for CoreCLR, a catchpad which immediately executes an `unreachable` instruction indicates that the exception can never have a matching type, and so such catchpads can be removed, and so can their catchswitches if the catchswitch becomes empty. Reviewers: rnk, andrew.w.kaylor, majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15846 llvm-svn: 256809
* Revert "[X86] Use push-pop for materializing small constants under 'minsize'"David Majnemer2016-01-053-186/+102
| | | | | | | | | | | | The red zone consists of 128 bytes beyond the stack pointer so that the allocation of objects in leaf functions doesn't require decrementing rsp. In r255656, we introduced an optimization that would cheaply materialize certain constants via push/pop. Push decrements the stack pointer and stores it's result at what is now the top of the stack. However, this means that using push/pop would encroach on the red zone. PR26023 gives an example where this corrupts an object in the red zone. llvm-svn: 256808
* X86: Add a testcase for PR25951Matthias Braun2016-01-051-0/+54
| | | | llvm-svn: 256801
* MachineInstrBundle: Fix reversed isSuperRegisterEq() callMatthias Braun2016-01-052-10/+20
| | | | | | | | | | | | | | | Unfortunately this fix had the effect of exposing the -verify-machineinstrs FIXME of X86InstrInfo.cpp in two testcases for which I disabled it for now. Two testcases also have additional pushq/popq where the corrected code cannot prove that %rax is dead any longer. Looking at the examples, this could potentially be fixed by improving computeRegisterLiveness() to check the live-in lists of the successors blocks when reaching the end of a block. This fixes http://llvm.org/PR25951. llvm-svn: 256799
* AMDGPU: add +xnack featureNicolai Haehnle2016-01-041-6/+11
| | | | | | | | | | | | | | | | | | | Summary: Enabling this feature will account for the two SGPRs used by the hardware to store the XNACK_MASK physically. The hardware only requires this reservation when the XNACK feature is explicitly enabled. At some point, HSA will probably want to do that, but it does increase SGPR register pressure, so leave it disabled by default for now (but do add a small test). Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15869 llvm-svn: 256794
* [InstructionCombining] prepareICWorklistFromFunction halts in infinite loop ↵Chen Li2016-01-041-0/+17
| | | | | | | | | | | | | | with instructions of token type Summary: This patch fixes a bug in prepareICWorklistFromFunction, where the loop becomes infinite with instructions of token type. The patch checks if the instruction is token type, and if so it updates EndInst with the current instruction. Reviewers: reames, majnemer Subscribers: llvm-commits, sanjoy Differential Revision: http://reviews.llvm.org/D15859 llvm-svn: 256792
* [LICM] Fix a small oversight introduced in r256763David Majnemer2016-01-041-0/+4
| | | | | | | | | | | r256763 had promoteLoopAccessesToScalars check for the existence of a catchswitch when the exit blocks were populated but promoteLoopAccessesToScalars may be called with a prepopulated set of exit blocks which would also need to be checked. This fixes PR26019. llvm-svn: 256788
* [MemoryBuiltins] Remove isOperatorNewLike by consolidating non-null ↵Philip Reames2016-01-042-1/+7
| | | | | | | | | | | | inference handling This patch removes the isOperatorNewLike predicate since it was only being used to establish a non-null return value and we have attributes specifically for that purpose with generic handling. To keep approximate the same behaviour for existing frontends, I added the various operator new like (i.e. instances of operator new) to InferFunctionAttrs. It's not really clear to me why this isn't handled in Clang, but I didn't want to break existing code and any subtle assumptions it might have. Once this patch is in, I'm going to start separating the isAllocLike family of predicates. These appear to be being used for a mixture of things which should be more clearly separated and documented. Today, they're being used to indicate (at least) aliasing facts, CSE-ability, and default values from an allocation site. Differential Revision: http://reviews.llvm.org/D15820 llvm-svn: 256787
* [X86][SSE] Ensure BLENDPD/BLENDPS/PBLEND inputs are both of the correct ↵Simon Pilgrim2016-01-041-55/+29
| | | | | | input type llvm-svn: 256782
* Remove dead instructions before RedoingAditya Nandakumar2016-01-042-1/+35
| | | | | | | | | Before reevaluating instructions, iterate over all instructions to be reevaluated and remove trivially dead instructions and if any of it's operands become trivially dead, mark it for deletion until all trivially dead instructions have been removed llvm-svn: 256773
* [AArch64] Optimize some simple TBZ/TBNZ cases.Geoff Berry2016-01-041-0/+103
| | | | | | | | | | | | | | | | | | Summary: Add some AArch64 dag combines to optimize some simple TBZ/TBNZ cases: (tbz (and x, m), b) -> (tbz x, b) (tbz (shl x, c), b) -> (tbz x, b-c) (tbz (shr x, c), b) -> (tbz x, b+c) (tbz (xor x, -1), b) -> (tbnz x, b) Reviewers: jmolloy, mcrosier, t.p.northover Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D15702 llvm-svn: 256765
* [LICM] Don't insert instructions after a catchswitch when performing loop ↵David Majnemer2016-01-041-0/+36
| | | | | | | | | promotion Inserting after a catchswitch results in verifier errors, bail out on promotion if a catchswitch is a loop exit. llvm-svn: 256763
* [WinEH] Update CoreCLR EH state numberingJoseph Tremoulet2016-01-041-100/+525
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Fix the CLR state numbering to generate correct tables, and update the lit test to verify them. The CLR numbering assigns one state number to each catchpad and cleanuppad. It also computes two tree-like relations over states: 1) Each state has a "HandlerParentState", which is the state of the next outer handler enclosing this state's handler (same as nearest ancestor per the ParentPad linkage on EH pads, but skipping over catchswitches). 2) Each state has a "TryParentState", which: a) for a catchpad that's not the last handler on its catchswitch, is the state of the next catchpad on that catchswitch. b) for all other pads, is the state of the pad whose try region is the next outer try region enclosing this state's try region. The "try regions are not present as such in the IR, but will be inferred based on the placement of invokes and pads which reach each other by exceptional exits. Catchswitches do not get their own states, but each gets mapped to the state of its first catchpad. Table generation requires each state's "unwind dest" state to have a lower state number than the given state. Since HandlerParentState can be computed as a function of a pad's ParentPad, and TryParentState can be computed as a function of its unwind dest and the TryParentStates of its children, the CLR state numbering algorithm first computes HandlerParentState in a top-down pass, then computes TryParentState in a bottom-up pass. Also reword some comments/names in the CLR EH table generation to make the distinction between the different kinds of "parent" clear. Reviewers: rnk, andrew.w.kaylor, majnemer Subscribers: AndyAyers, llvm-commits Differential Revision: http://reviews.llvm.org/D15325 llvm-svn: 256760
* [AVX512] add PSRAD and PSRAQ IntrinsicMichael Zuckerman2016-01-042-0/+209
| | | | | | Differential Revision: http://reviews.llvm.org/D15851 llvm-svn: 256754
* [AVX512] add PSRAW Intrinsic Michael Zuckerman2016-01-042-0/+122
| | | | | | Differential Revision: http://reviews.llvm.org/D15850 llvm-svn: 256751
* [AVX512] add PSRLV Intrinsic Michael Zuckerman2016-01-043-0/+145
| | | | | | Differential Revision: http://reviews.llvm.org/D15838 llvm-svn: 256747
* [LICM] Make instruction sinking funclet-awareDavid Majnemer2016-01-042-2/+69
| | | | | | | | | | | We had two bugs here: - We might try to sink into a catchswitch, causing verifier failures. - We will succeed in sinking into a cleanuppad but we didn't update the funclet operand bundle. This fixes PR26000. llvm-svn: 256728
* Fix one file that I didn't convert properly in r256707.Dimitry Andric2016-01-031-1/+1
| | | | llvm-svn: 256720
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