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| author | Geoff Berry <gberry@codeaurora.org> | 2016-01-06 18:14:26 +0000 |
|---|---|---|
| committer | Geoff Berry <gberry@codeaurora.org> | 2016-01-06 18:14:26 +0000 |
| commit | 12fe2279f3d166d4b1dfe302298fbf45c7afaf40 (patch) | |
| tree | 715ac92ed869ad392b698fad49515c4238ab8355 /llvm/test | |
| parent | fe46cadcf90386a958058fe4540b6ff2ff9c9ea1 (diff) | |
| download | bcm5719-llvm-12fe2279f3d166d4b1dfe302298fbf45c7afaf40.tar.gz bcm5719-llvm-12fe2279f3d166d4b1dfe302298fbf45c7afaf40.zip | |
ScheduleDAGInstrs: Bug fix for missed memory dependency.
Summary:
In buildSchedGraph(), when adding memory dependencies for loads, move
the call to adjustChainDeps() after the call to
addChainDependency(AliasChain) to handle the case where
addChainDependency(AliasChain) ends up not adding a dependency and
instead putting the SU on the RejectMemNodes list. The call to
adjustChainDeps() must be done after the call to addChainDependency() in
order to process the SU added to the RejectMemNodes list to create
memory dependencies for it.
Reviewers: hfinkel, atrick, jonpa, resistor
Subscribers: mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D15927
llvm-svn: 256950
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll b/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll new file mode 100644 index 00000000000..770521b7528 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll @@ -0,0 +1,22 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s +; +; Test for bug in misched memory dependency calculation. +; +; CHECK: ********** MI Scheduling ********** +; CHECK: misched_bug:BB#0 entry +; CHECK: SU(2): %vreg2<def> = LDRWui %vreg0, 1; mem:LD4[%ptr1_plus1] GPR32:%vreg2 GPR64common:%vreg0 +; CHECK: Successors: +; CHECK-NEXT: val SU(5): Latency=4 Reg=%vreg2 +; CHECK-NEXT: ch SU(4): Latency=0 +; CHECK: SU(4): STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1 +; CHECK: SU(5): %W0<def> = COPY %vreg2; GPR32:%vreg2 +; CHECK: ** ScheduleDAGMI::schedule picking next node +define i32 @misched_bug(i32* %ptr1, i32* %ptr2) { +entry: + %ptr1_plus1 = getelementptr inbounds i32, i32* %ptr1, i64 1 + %val1 = load i32, i32* %ptr1_plus1, align 4 + store i32 0, i32* %ptr1, align 4 + store i32 0, i32* %ptr2, align 4 + ret i32 %val1 +} |
