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* [PowerPC] Don't attempt a 64-bit pow2 division on PPC32Hal Finkel2014-12-231-0/+9
* [SimplifyCFG] Revise common code sinkingMichael Liao2014-12-231-2/+32
* [ARM] Don't break alignment when combining base updates into load/stores.Ahmed Bougacha2014-12-233-24/+105
* Revert r224739: Debug info: Teach SROA how to update debug info forChandler Carruth2014-12-233-203/+4
* X86: Don't over-align combined loads.Jim Grosbach2014-12-231-0/+35
* Make musttail more robust for vector types on x86Reid Kleckner2014-12-222-0/+116
* Thumb1 frame lowering: Mark CFI instructions with the FrameSetup flag.Adrian Prantl2014-12-221-1/+2
* [LCSSA] Handle PHI insertion in disjoint loopsBruno Cardoso Lopes2014-12-221-4/+36
* Debug info: Teach SROA how to update debug info for fragmented variables.Adrian Prantl2014-12-223-4/+203
* Fix Windows unwind info for functions in sections other than .textReid Kleckner2014-12-221-2/+72
* [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730.Colin LeMahieu2014-12-222-2/+14
* [Hexagon] Adding classes and load unsigned byte instruction, updating usages.Colin LeMahieu2014-12-221-0/+14
* [x86] Add vector @llvm.ctpop intrinsic custom loweringBruno Cardoso Lopes2014-12-221-0/+159
* [CodeGenPrepare] Handle properly the promotion of operands when this does notQuentin Colombet2014-12-221-0/+25
* AVX-512: Added all forms of BLENDM instructions,Elena Demikhovsky2014-12-223-2/+301
* Lower multiply-negate operation to mneg on AArch64Karthik Bhat2014-12-221-0/+15
* Convert a few tests to FileCheck. NFC.Rafael Espindola2014-12-224-14/+38
* Enable (sext x) == C --> x == (trunc C) combineMatt Arsenault2014-12-213-7/+542
* ARM: further improve deprecated diagnosis (LDM)Saleem Abdulrasool2014-12-201-5/+74
* This should have been part of r224676.David Majnemer2014-12-201-2/+2
* InstCombine: Squash an icmp+select into bitwise arithmeticDavid Majnemer2014-12-201-0/+33
* InstSimplify: Optimize away pointless comparisonsDavid Majnemer2014-12-201-0/+76
* [x86] Change the test added in r223774 to first check the spelling ofChandler Carruth2014-12-201-26/+33
* Masked load and store codegen - fixed 128-bit vectorsElena Demikhovsky2014-12-191-8/+78
* R600/SI: Only form min/max with 1 use.Matt Arsenault2014-12-193-0/+69
* Add printing the LC_ROUTINES load commands with llvm-objdump’s -private-hea...Kevin Enderby2014-12-192-0/+14
* Add the ExceptionHandling::MSVC enumerationReid Kleckner2014-12-194-4/+4
* Model sqrtss as a binary operation with one source operand tied to the destin...Sanjay Patel2014-12-191-5/+38
* R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operandTom Stellard2014-12-191-0/+39
* Add printing the LC_SUB_CLIENT load command with llvm-objdump’s -private-he...Kevin Enderby2014-12-192-0/+7
* CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.Peter Collingbourne2014-12-191-0/+19
* [Hexagon] Removing old variants of instructions and updating references.Colin LeMahieu2014-12-191-0/+2
* merge consecutive stores of extracted vector elementsSanjay Patel2014-12-191-0/+33
* [Hexagon] Adding bit extraction and table indexing instructions.Colin LeMahieu2014-12-191-0/+16
* [Hexagon] Adding bit insertion instructions.Colin LeMahieu2014-12-191-0/+8
* [Hexagon] Adding more xtype shift instructions.Colin LeMahieu2014-12-192-0/+22
* Add printing the LC_SUB_LIBRARY load command with llvm-objdump’s -private-h...Kevin Enderby2014-12-192-0/+7
* [Hexagon] Adding xtype shift instructions.Colin LeMahieu2014-12-192-0/+132
* [Hexagon] Adding transfers to and from control registers.Colin LeMahieu2014-12-191-1/+5
* Reapply: [InstCombine] Fix visitSwitchInst to use right operand types for sub...Bruno Cardoso Lopes2014-12-191-0/+30
* use -0.0 when creating an fneg instructionSanjay Patel2014-12-191-1/+1
* Revert "[InstCombine] Fix visitSwitchInst to use right operand types for sub ...Bruno Cardoso Lopes2014-12-191-30/+0
* [InstCombine] Fix visitSwitchInst to use right operand types for sub cstexprBruno Cardoso Lopes2014-12-191-0/+30
* [Object] Don't crash on empty export lists.Juergen Ributzka2014-12-192-0/+4
* [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.Colin LeMahieu2014-12-191-0/+20
* ConstantFold: Shifting undef by zero results in undefDavid Majnemer2014-12-181-0/+21
* Reverting 224550, was not ready for commit.Colin LeMahieu2014-12-181-20/+0
* [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.Colin LeMahieu2014-12-181-0/+20
* Add printing the LC_SUB_UMBRELLA load command with llvm-objdump’s -private-...Kevin Enderby2014-12-182-0/+7
* Add printing the LC_SUB_FRAMEWORK load command with llvm-objdump’s -private...Kevin Enderby2014-12-182-0/+7
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