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* [llvm-mca] Support for in-order CPU for -instruction-tables testing.Andrea Di Biagio2018-04-307-0/+3787
* [llvm-mca][X86] Add BT resource tests to all modelsSimon Pilgrim2018-04-298-8/+1184
* [llvm-mca][X86] Add add/adc + sub/sbb resource tests to all modelsSimon Pilgrim2018-04-298-8/+3016
* [llvm-mca][X86] Add double shift resource tests to all relevant modelsSimon Pilgrim2018-04-288-8/+608
* [llvm-mca][X86] Add shift/rotate resource tests to all relevant modelsSimon Pilgrim2018-04-288-0/+4386
* [llvm-mca][X86] Updated fma3 tests after rL330820Simon Pilgrim2018-04-252-10/+10
* [llvm-mca] Default to the native host cpu if flag -mcpu is not specified.Andrea Di Biagio2018-04-251-1/+0
* [X86] Split off PHMINPOSUW to their own schedule classSimon Pilgrim2018-04-242-6/+6
* [X86][F16C] Add WriteCvtF2FSt scheduling classSimon Pilgrim2018-04-241-5/+5
* [X86][BtVer2] Fix VCVTPS2PHmr/VCVTPS2PHYmr latenciesSimon Pilgrim2018-04-241-11/+5
* [X86][IVB] Add F16C resource tests.Simon Pilgrim2018-04-241-0/+58
* [llvm-mca] Default the output asm dialect used by the instruction printer to ...Andrea Di Biagio2018-04-241-0/+37
* [X86] Remove unnecessary FMA reg-mem InstRW scheduler overrides.Simon Pilgrim2018-04-242-4/+4
* [X86] Add vector element insertion/extraction scheduler classesSimon Pilgrim2018-04-242-10/+10
* [llvm-mca][X86] Add BMI/LZCNT/POPCNT resource tests to all relevant modelsSimon Pilgrim2018-04-2225-0/+2322
* [X86] Remove unnecessary WriteFVarBlend/WriteVarBlend InstRW overrides.Simon Pilgrim2018-04-222-28/+30
* [llvm-mca][X86] Add POPCNT resource testSimon Pilgrim2018-04-222-0/+108
* [llvm-mca][X86] Add AVX2 resource testsSimon Pilgrim2018-04-215-0/+5387
* [llvm-mca][X86] Add SSE resource tests to all modelsSimon Pilgrim2018-04-2135-0/+13352
* [llvm-mca][X86] Add MMX resource testsSimon Pilgrim2018-04-216-0/+2376
* [llvm-mca][X86] Add X87 resource testsSimon Pilgrim2018-04-218-0/+4194
* [llvm-mca][X86] Add MMX/SSE/AES/CLMUL resource SandyBridge testsSimon Pilgrim2018-04-209-0/+2733
* [llvm-mca][X86] Add prefetch instruction resource testsSimon Pilgrim2018-04-191-1/+14
* [llvm-mca][FMA] Add FMA resource testsSimon Pilgrim2018-04-195-0/+3522
* [llvm-mca][X86] Add resource test for every out-of-order scheduler modelSimon Pilgrim2018-04-197-0/+14536
* [llvm-mca][X86] Add mmx instruction to btver2 resource testsSimon Pilgrim2018-04-193-8/+569
* [llvm-mca][X86] Add mmx versions of SSSE3 instructionsSimon Pilgrim2018-04-182-23/+135
* [UpdateTestChecks] Add update_mca_test_checks.py scriptGreg Bedwell2018-04-1834-166/+1025
* [X86] Add separate scheduling class for PSADBW instruction.Craig Topper2018-04-171-2/+2
* [llvm-mca] Ensure that instructions with a schedule read-advance are always i...Andrea Di Biagio2018-04-131-0/+44
* [llvm-mca] Renamed BackendStatistics to RetireControlUnitStatistics.Andrea Di Biagio2018-04-111-0/+56
* [llvm-mca] Move the logic that prints scheduler statistics from BackendStatis...Andrea Di Biagio2018-04-112-5/+35
* [llvm-mca] Move the logic that prints dispatch unit statistics from BackendSt...Andrea Di Biagio2018-04-105-5/+5
* [llvm-mca] Increase the default number of iterations to 100.Andrea Di Biagio2018-04-104-55/+144
* Reapply "[llvm-mca] Do not separate iterations with a newline in the timeline...Andrea Di Biagio2018-04-109-30/+30
* [llvm-mca] Add the ability to mark regions of code for analysis (PR36875)Andrea Di Biagio2018-04-097-0/+185
* Revert r329403 "[llvm-mca] Do not separate iterations with a newline in the t...Hans Wennborg2018-04-099-30/+30
* [X86][Btver2] Add vector extract costsSimon Pilgrim2018-04-083-30/+30
* [llvm-mca] Do not separate iterations with a newline in the timeline view.Andrea Di Biagio2018-04-069-30/+30
* [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca. Andrea Di Biagio2018-04-053-49/+47
* [X86][Btver2] Strip unnecessary check prefixes from resources testsSimon Pilgrim2018-04-0411-11/+11
* [llvm-mca] Move the logic that prints register file statistics to its own vie...Andrea Di Biagio2018-04-035-5/+5
* [MC][Tablegen] Allow the definition of processor register files in the schedu...Andrea Di Biagio2018-04-035-13/+217
* [llvm-mca] Do not assume that implicit reads cannot be associated with ReadAd...Andrea Di Biagio2018-04-021-0/+26
* [X86] Add SchedRW for PMULLDCraig Topper2018-03-313-29/+28
* [X86][BtVer2] Fixed the number of micro opcodes for AVX vector converts andAndrea Di Biagio2018-03-301-8/+8
* [X86][BtVer2] Fix the number of uOps for horizontal operations.Andrea Di Biagio2018-03-302-12/+12
* [X86][BtVer2] Add missing ReadAfterLd to RM variants of AVX horizontal adds andAndrea Di Biagio2018-03-303-12/+10
* [X86][BtVer2] Add tests that show how ReadAfterLd is missing for someAndrea Di Biagio2018-03-304-0/+92
* [X86] Add llvm-mca tests for r328834.Andrea Di Biagio2018-03-304-0/+120
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