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* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-141-0/+26
* [X86] AMD Znver2 (Rome) Scheduler enablementGanesh Gopalasubramanian2020-01-1055-6/+12598
* [MCA] Fix test cases (NFC)Evandro Menezes2019-11-2210-30/+30
* [AArch64] Add the pipeline model for Exynos M5Evandro Menezes2019-11-2228-34/+2335
* Revert "[AArch64] Add the pipeline model for Exynos M5"Eric Christopher2019-11-2028-2335/+34
* [AArch64] Add the pipeline model for Exynos M5Evandro Menezes2019-11-2028-34/+2335
* [X86] Fix SLM v2i64 ADD/Sub/CMPEQ instruction schedulesSimon Pilgrim2019-11-062-14/+14
* [X86] Fix SLM v2f64 ADD/MUL + FP BLEND/HADD instruction schedulesSimon Pilgrim2019-11-063-43/+43
* [mca] Fix test case (NFC)Evandro Menezes2019-10-311-6/+6
* [AArch64] Update for ExynosEvandro Menezes2019-10-311-0/+71
* [clang][llvm] Obsolete Exynos M1 and M2Evandro Menezes2019-10-304-46/+0
* [X86][BtVer2] Improved latency and throughput of float/vector loads and stores.Andrea Di Biagio2019-10-147-59/+59
* [MCA] Show aggregate over Average Wait times for the whole snippet (PR43219)Roman Lebedev2019-10-10150-0/+296
* [MCA][LSUnit] Track loads and stores until retirement.Andrea Di Biagio2019-10-083-75/+72
* [llvm-mca] Add a -mattr flagDavid Green2019-10-011-0/+29
* [MCA] Improved cost computation for loop carried dependencies in the bottlene...Andrea Di Biagio2019-09-191-8/+4
* [X86][BtVer2] Fix latency and throughput of conditional SIMD store instructions.Andrea Di Biagio2019-09-022-14/+14
* [X86][BtVer2] Add a read-advance to every implicit register use of CMPXCHG8B/...Andrea Di Biagio2019-08-231-0/+304
* [X86][BtVer2] Fix latency of ALU RMW instructions.Andrea Di Biagio2019-08-231-222/+222
* [X86][BtVer2] Fix latency/throughput of scalar integer MUL instructions.Andrea Di Biagio2019-08-2215-246/+247
* [X86][BtVer2] Fix latency and throughput of XCHG and XADD.Andrea Di Biagio2019-08-223-55/+328
* [X86][BtVer2] Use ReadAfterLd entries for the register operands of CMPXCHG.Andrea Di Biagio2019-08-201-0/+286
* [X86][BtVer2] Fix latency and throughput of atomic INC/DEC/NEG/NOT.Andrea Di Biagio2019-08-201-33/+33
* [MCA][X86] Add tests for LOCK variants of standard X86 arithmetic opsSimon Pilgrim2019-08-2012-24/+4596
* [X86][Btver2] Fix latency and throughput of CMPXCHG instructions.Andrea Di Biagio2019-08-202-34/+34
* [X86] Move scheduling tests for CMPXCHG to the corresponding resources-x86_64...Andrea Di Biagio2019-08-1924-492/+168
* [X86] Added extensive scheduling model tests for all the CMPXCHG variants. NFCAndrea Di Biagio2019-08-1912-12/+552
* [MCA] Add flag -show-encoding to llvm-mca.Andrea Di Biagio2019-08-091-0/+77
* [X86] Limit vpermil2pd/vpermil2ps immediates to 4 bits in the assembly parser.Craig Topper2019-08-072-12/+12
* [MCA] Add support for printing immedate values as hex. Also enable lexing of ...Andrea Di Biagio2019-08-022-0/+69
* Set an explicit x86 triple for test bottleneck-analysis.s added by my r364045...Andrea Di Biagio2019-06-211-1/+1
* [MCA][Bottleneck Analysis] Teach how to compute a critical sequence of instru...Andrea Di Biagio2019-06-218-0/+321
* Fix r363773: Update Barcelona MCA tests.Clement Courbet2019-06-191-2/+2
* [NFC][X86][MCA] Barcelona: add load/store/load-store-throughput testsRoman Lebedev2019-06-193-0/+1855
* [NFC][X86][MCA] BdVer2: add load-store-throughput testRoman Lebedev2019-06-191-0/+736
* [X86] Add missing properties on llvm.x86.sse.{st,ld}mxcsrClement Courbet2019-06-1922-46/+46
* [lit] Delete empty lines at the end of lit.local.cfg NFCFangrui Song2019-06-173-3/+0
* [NFC][MCA][X86] Add one more 'clear super register' pattern - movss/movsd loa...Roman Lebedev2019-06-152-0/+230
* [NFC][MCA][X86] Add baseline test coverage for AMD Barcelona (aka K10, fam10h)Roman Lebedev2019-06-1548-120/+8928
* [llvm-mca] Enable bottleneck analysis when flag -all-views is specified.Andrea Di Biagio2019-06-104-1/+22
* [MCA][Scheduler] Improved critical memory dependency computation.Andrea Di Biagio2019-05-261-1/+1
* [X86] Add zero idioms to the haswell, broadwell, and skylake schedule models....Craig Topper2019-05-255-1405/+1405
* [X86][llvm-mca] Add zero idiom tests for Intel CPUs. NFCCraig Topper2019-05-255-44/+2296
* [MCA] Add support for nested and overlapping region markersAndrea Di Biagio2019-05-097-4/+265
* [X86] AMD Piledriver (BdVer2): major cleanup (mainly inverse throughput)Roman Lebedev2019-05-0981-6232/+6237
* [MCA] Don't add a name to the default code region.Andrea Di Biagio2019-05-081-1/+1
* [X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly prin...Craig Topper2019-05-0633-176/+176
* [llvm-mca][x86] Fix MMX PMOVMSKB testSimon Pilgrim2019-04-2911-33/+33
* [MCA] Fix typo in AVX2 gather tests. NFCAndrea Di Biagio2019-04-286-18/+18
* [MCA] Remove wrong comments from a test. NFCAndrea Di Biagio2019-04-111-3/+0
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