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* [MCA][X86] Add tests for LOCK variants of standard X86 arithmetic opsSimon Pilgrim2019-08-201-1/+382
| | | | | | D66424 adds the base support for LOCK so we should be able to add special case support for all these cases in future patches llvm-svn: 369367
* [X86] Move scheduling tests for CMPXCHG to the corresponding ↵Andrea Di Biagio2019-08-191-1/+13
| | | | | | | | | | resources-x86_64.s files. NFC In D66424 it has been requested to move all the new tests added by r369278 into resources-x86_64.s. That is because only the 8b/16 ops should be tested by resources-cmpxchg.s. This partially reverts r369278. llvm-svn: 369288
* [X86] Correct scheduler information for rotate by constant for Haswell, ↵Craig Topper2019-03-071-17/+17
| | | | | | | | | | | | | | Broadwell, and Skylake. Rotate with explicit immediate is a single uop from Haswell on. An immediate of 1 has a dependency on the previous writer of flags, but the other immediate values do not. The implicit rotate by 1 instruction is 2 uops. But the flags are merged after the rotate uop so the data result does not see the flag dependency. But I don't think we have any way of modeling that. RORX is 1 uop without the load. 2 uops with the load. We currently model these with WriteShift/WriteShiftLd. Differential Revision: https://reviews.llvm.org/D59077 llvm-svn: 355636
* [X86] Model ADC/SBB with immediate 0 more accurately in the Haswell ↵Craig Topper2019-03-071-13/+13
| | | | | | | | | | scheduler model Haswell and possibly Sandybridge have an optimization for ADC/SBB with immediate 0 to use a single uop flow. This only applies GR16/GR32/GR64 with an 8-bit immediate. It does not apply to GR8. It also does not apply to the implicit AX/EAX/RAX forms. Differential Revision: https://reviews.llvm.org/D59058 llvm-svn: 355635
* [llvm-mca][X86] Add ADC/SBB with zero test casesSimon Pilgrim2019-03-061-1/+73
| | | | | | Some targets have fast-path handling for these patterns that we should model. llvm-svn: 355498
* [llvm-mca][X86] Add missing enter/leave, invlpg/invlpga, rdmsr/wrmsr, rdpmc ↵Simon Pilgrim2019-01-221-1/+33
| | | | | | and rdtsc/rdtscp tests llvm-svn: 351835
* [X86] ROR*mCL instruction models should match ROL*mCL etc.Simon Pilgrim2018-09-231-9/+9
| | | | | | | | Confirmed with Craig Topper - fix a typo that was missing a Port4 uop for ROR*mCL instructions on some Intel models. Yet another step on the scheduler model cleanup marathon...... llvm-svn: 342846
* [X86] MCA tests for XCHG*, XADD* and CMPXCHG* instructionsAndrew V. Tischenko2018-08-071-1/+94
| | | | | | Differential Revision: https://reviews.llvm.org/D49912 llvm-svn: 339145
* [llvm-mca][x86] Add SET/TEST instruction resource testsSimon Pilgrim2018-08-011-1/+180
| | | | llvm-svn: 338576
* [llvm-mca][x86] Add more x86-64 system instruction resource testsSimon Pilgrim2018-08-011-1/+92
| | | | | | CPUID, IN/OUT, INS/OUTS, INT, PAUSE, SCAS, UD2, XLAT llvm-svn: 338563
* [llvm-mca][x86] Add CMPS/LODS/MOVS/STOS string instruction resource testsSimon Pilgrim2018-08-011-1/+53
| | | | llvm-svn: 338532
* [llvm-mca][x86] Add STC + STD instruction resource testsSimon Pilgrim2018-08-011-1/+8
| | | | llvm-svn: 338514
* [llvm-mca][x86] Add movsx/movzx instructions to general x86_64 resource testsSimon Pilgrim2018-07-201-1/+70
| | | | llvm-svn: 337586
* [llvm-mca][x86] Add extend, carry-flag and CMP instructions to general ↵Simon Pilgrim2018-07-171-1/+120
| | | | | | x86_64 resource tests llvm-svn: 337306
* [llvm-mca][x86] Add BSWAP resource testsSimon Pilgrim2018-07-171-1/+8
| | | | llvm-svn: 337302
* [llvm-mca] Use a different character to flag instructions with side-effects ↵Andrea Di Biagio2018-07-111-18/+18
| | | | | | | | | | | | | | | | | | | | | in the Instruction Info View. NFC This makes easier to identify changes in the instruction info flags. It also helps spotting potential regressions similar to the one recently introduced at r336728. Using the same character to mark MayLoad/MayStore/HasSideEffects is problematic for llvm-lit. When pattern matching substrings, llvm-lit consumes tabs and spaces. A change in position of the flag marker may not trigger a test failure. This patch only changes the character used for flag `hasSideEffects`. The reason why I didn't touch other flags is because I want to avoid spamming the mailing because of the massive diff due to the numerous tests affected by this change. In future, each instruction flag should be associated with a different character in the Instruction Info View. llvm-svn: 336797
* [MCA][X86][NFC] Add BSF/BSR resource testsRoman Lebedev2018-07-081-1/+40
| | | | | | | | | | | | Reviewers: RKSimon, andreadb, courbet Reviewed By: RKSimon Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D48997 llvm-svn: 336510
* [X86] Add sched class WriteLAHFSAHF and fix values.Clement Courbet2018-06-201-1/+9
| | | | | | | | | | | | | | | Summary: I ran llvm-exegesis on SKX, SKL, BDW, HSW, SNB. Atom is from Agner and SLM is a guess. I've left AMD processors alone. Reviewers: RKSimon, craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D48079 llvm-svn: 335097
* [X86] Fix NOOP sched overrides on BDW/HSW/SKL.Clement Courbet2018-06-181-8/+8
| | | | | | | | | | | | Summary: Noop certainly does not use resources. Reviewers: RKSimon, craig.topper, andreadb Subscribers: gbedwell, llvm-commits, gchatelet Differential Revision: https://reviews.llvm.org/D48028 llvm-svn: 334927
* [llvm-mca][x86] Fix all resources-x86_64.s tests to use different registers ↵Simon Pilgrim2018-06-061-195/+195
| | | | | | | | in reg-reg cases I noticed while working on zero-idiom + dependency-breaking support (PR36671) that most of our binary instruction tests were reusing the same src registers, which would cause the tests to fail once we enable scalar zero-idiom support on btver2. Fixed in all targets to keep them in sync. llvm-svn: 334110
* [CodeGen] assume max/default throughput for unspecified instructionsSanjay Patel2018-06-051-13/+13
| | | | | | | | | | | | | This is a fix for the problem arising in D47374 (PR37678): https://bugs.llvm.org/show_bug.cgi?id=37678 We may not have throughput info because it's not specified in the model or it's not available with variant scheduling, so assume that those instructions can execute/complete at max-issue-width. Differential Revision: https://reviews.llvm.org/D47723 llvm-svn: 334055
* [llvm-mca] Make sure not to end the test files with an empty line.Roman Lebedev2018-06-041-1/+0
| | | | | | | | | | | | | | | | | | | Summary: It's super irritating. [properly configured] git client then complains about that double-newline, and you have to use `--force` to ignore the warning, since even if you fix it manually, it will be reintroduced the very next runtime :/ Reviewers: RKSimon, andreadb, courbet, craig.topper, javed.absar, gbedwell Reviewed By: gbedwell Subscribers: javed.absar, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47697 llvm-svn: 333887
* [X86][Sched] Add InstRW for CLC on Intel after SNB.Clement Courbet2018-05-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: After SNB, Intel CPUs can rename CF independently of other EFLAGS, so the renamer can zero it for free. Note that STC still consumes resources. To reproduce: `$ llvm-exegesis -mode=uops -opcode-name=CLC` On SNB: ``` --- key: opcode_name: CLC mode: uops config: '' cpu_name: sandybridge llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: '3', value: 0.0014, debug_string: SBPort0 } - { key: '4', value: 0.0013, debug_string: SBPort1 } - { key: '5', value: 0.0003, debug_string: SBPort4 } - { key: '6', value: 0.0029, debug_string: SBPort5 } - { key: '10', value: 0.0003, debug_string: SBPort23 } error: '' info: 'instruction is serial, repeating a random one. Snippet: CLC ' ... ``` On HSW: ``` --- key: opcode_name: CLC mode: uops config: '' cpu_name: haswell llvm_triple: x86_64-unknown-linux-gnu num_repetitions: 10000 measurements: - { key: '3', value: 0.001, debug_string: HWPort0 } - { key: '4', value: 0.0009, debug_string: HWPort1 } - { key: '5', value: 0.0004, debug_string: HWPort2 } - { key: '6', value: 0.0006, debug_string: HWPort3 } - { key: '7', value: 0.0002, debug_string: HWPort4 } - { key: '8', value: 0.0012, debug_string: HWPort5 } - { key: '9', value: 0.0022, debug_string: HWPort6 } - { key: '10', value: 0.0001, debug_string: HWPort7 } error: '' info: 'instruction is serial, repeating a random one. Snippet: CLC ' ... ``` Reviewers: craig.topper, RKSimon Subscribers: gchatelet, llvm-commits Differential Revision: https://reviews.llvm.org/D47362 llvm-svn: 333392
* [llvm-mca] Regenerate tests after r332381 and r332361. NFCAndrea Di Biagio2018-05-161-1090/+1090
| | | | llvm-svn: 332447
* [llvm-mca][x86] Add and/not/or/xor instruction testsSimon Pilgrim2018-05-141-1/+308
| | | | llvm-svn: 332257
* [llvm-mca][x86] Add div/idiv, mul/imul and inc/dec/neg/nop instruction testsSimon Pilgrim2018-05-081-1/+255
| | | | llvm-svn: 331765
* [llvm-mca][X86] Add BT resource tests to all modelsSimon Pilgrim2018-04-291-1/+148
| | | | llvm-svn: 331144
* [llvm-mca][X86] Add add/adc + sub/sbb resource tests to all modelsSimon Pilgrim2018-04-291-1/+377
| | | | llvm-svn: 331140
* [llvm-mca][X86] Add double shift resource tests to all relevant modelsSimon Pilgrim2018-04-281-1/+76
| | | | llvm-svn: 331109
* [llvm-mca][X86] Add shift/rotate resource tests to all relevant modelsSimon Pilgrim2018-04-281-0/+548
I intend to add further instruction tests to the resources-x86_64.s test file as required, but this initial commit is to help remove a load of unnecessary InstRW overrides in a future patch llvm-svn: 331108
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