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* [X86][BtVer2] Improved latency and throughput of float/vector loads and stores.Andrea Di Biagio2019-10-141-34/+34
* [X86][BtVer2] Fix latency and throughput of conditional SIMD store instructions.Andrea Di Biagio2019-09-021-11/+11
* [X86] Add missing properties on llvm.x86.sse.{st,ld}mxcsrClement Courbet2019-06-191-2/+2
* [X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly prin...Craig Topper2019-05-061-8/+8
* [X86] Remove the _alt forms of (V)CMP instructions. Use a combination of cust...Craig Topper2019-03-181-24/+24
* [X86][Btver2] Improved latency/throughput model for scalar int-to-float conve...Andrea Di Biagio2019-01-291-8/+8
* [X86][BtVer2] SSE2 vector shifts has local forwarding disabledSimon Pilgrim2019-01-221-24/+24
* [X86][BtVer2] X86ISD::VPERMILPV has local forwarding disabledSimon Pilgrim2019-01-221-8/+8
* [X86][BtVer2] Update the WriteLoad latency.Andrea Di Biagio2019-01-211-1/+1
* [X86][BtVer2] Update latency of horizontal operations.Andrea Di Biagio2019-01-161-28/+28
* [X86][Btver2] Fix BLENDV and AESDEC schedulesSimon Pilgrim2018-10-021-19/+19
* [X86][Btver2] Fix masked load scheduleSimon Pilgrim2018-10-011-5/+5
* [LLVM-MCA][X86] Add missing VCMPESTR/VCMPESTR testsSimon Pilgrim2018-09-301-1/+29
* [X86][Btver2] CVTSS2I/CVTSD2I - add missing JFPU0 pipeSimon Pilgrim2018-09-281-17/+17
* [X86][BtVer2] Fix PHMINPOS schedule resources typoSimon Pilgrim2018-09-281-4/+4
* [X86][Btver2] (V)MPSADBW instructions take 3uops not 1Simon Pilgrim2018-09-271-2/+2
* [X86][BtVer2] Fix WriteFShuffle256 schedule write info.Andrea Di Biagio2018-08-311-11/+11
* [X86] Fix MayLoad/HasSideEffect flag for (V)MOVLPSrm instructions.Andrea Di Biagio2018-07-111-1/+1
* [llvm-mca] Use a different character to flag instructions with side-effects i...Andrea Di Biagio2018-07-111-7/+7
* [CodeGen] assume max/default throughput for unspecified instructionsSanjay Patel2018-06-051-2/+2
* [llvm-mca] Make sure not to end the test files with an empty line.Roman Lebedev2018-06-041-1/+0
* [X86] Add GPR<->XMM Schedule TagsSimon Pilgrim2018-05-181-9/+9
* [X86][BtVer2] Improve simulation of (V)PINSR valuesSimon Pilgrim2018-05-181-8/+8
* [X86][BtVer2] Partial vector stores (inc MMX) have a 2cy latencySimon Pilgrim2018-05-181-8/+8
* [X86][SSE] Ensure vector partial load/stores use the WriteVecLoad/WriteVecSto...Simon Pilgrim2018-05-181-5/+5
* [X86][SSE] Ensure float load/stores use the WriteFLoad/WriteFStore scheduler ...Simon Pilgrim2018-05-181-9/+9
* [llvm-mca] Regenerate tests after r332381 and r332361. NFCAndrea Di Biagio2018-05-161-1382/+1382
* [X86] Split WriteCvtF2F into F32->F64 and F64->F32 scheduler classesSimon Pilgrim2018-05-151-7/+7
* [X86][BtVer2] Fix MMX/YMM integer vector nt store schedulesSimon Pilgrim2018-05-141-1/+1
* [X86][BtVer2] Model ymm move as double pumped instructionsSimon Pilgrim2018-05-111-13/+13
* [X86] Add SchedWriteFRnd fp rounding scheduler classesSimon Pilgrim2018-05-041-9/+9
* [X86] Split off PHMINPOSUW to their own schedule classSimon Pilgrim2018-04-241-3/+3
* [UpdateTestChecks] Add update_mca_test_checks.py scriptGreg Bedwell2018-04-181-2/+6
* [X86] Add separate scheduling class for PSADBW instruction.Craig Topper2018-04-171-2/+2
* [X86][Btver2] Add vector extract costsSimon Pilgrim2018-04-081-20/+20
* [X86][Btver2] Strip unnecessary check prefixes from resources testsSimon Pilgrim2018-04-041-1/+1
* [X86] Add SchedRW for PMULLDCraig Topper2018-03-311-4/+4
* [X86][BtVer2] Fixed the number of micro opcodes for AVX vector converts andAndrea Di Biagio2018-03-301-8/+8
* [X86][BtVer2] Fix the number of uOps for horizontal operations.Andrea Di Biagio2018-03-301-8/+8
* [X86][BtVer2] Fix the number of micro opcodes for AES[ENC|DEC] and other YMM ...Andrea Di Biagio2018-03-281-22/+22
* [X86][BtVer2] Fix the number of micro opcodes for a bunch of YMM instructions.Andrea Di Biagio2018-03-281-0/+695
* [X86][Btver2] Add (U)COMISD/(U)COMISD scheduler costsSimon Pilgrim2018-03-261-8/+8
* [X86][Btver2] Add CVTSD2SS/CVTSS2SD scheduler costsSimon Pilgrim2018-03-261-4/+4
* [X86][Btver2] Account for the "+i" integer pipe transfer costs (1cy use of JA...Simon Pilgrim2018-03-261-17/+17
* [X86][Btver2] Add CVTSD2SI/CVTSS2SI scheduler costsSimon Pilgrim2018-03-261-12/+21
* [X86][Btver2] Fix YMM BLENDPD/BLENDPS + UNPCKPD/UNPCKP instructions costsSimon Pilgrim2018-03-261-12/+12
* [X86][Btver2] Add (V)SQRTPD/(V)SQRTSD costsSimon Pilgrim2018-03-261-4/+4
* [X86][Btver2] Double the AGU and schedule pipe resources for YMMSimon Pilgrim2018-03-261-103/+103
* [llvm-mca] Add flag -instruction-tables to print the theoretical resource pre...Andrea Di Biagio2018-03-261-389/+389
* [X86][Btver2] Cleanup TEST instructions to use JFPA (+JFPX on ymms) function ...Simon Pilgrim2018-03-231-33/+33
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