| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [X86] AMD Piledriver (BdVer2): major cleanup (mainly inverse throughput) | Roman Lebedev | 2019-05-09 | 1 | -37/+37 |
| * | [llvm-mca] Correctly update the resource strategy for processor resources wit... | Andrea Di Biagio | 2018-11-12 | 1 | -6/+6 |
| * | [X86][BdVer2] Fix loads/stores throughput for Piledriver (PR39465) | Roman Lebedev | 2018-11-10 | 1 | -12/+15 |
| * | AMD BdVer2 (Piledriver) Initial Scheduler model | Roman Lebedev | 2018-10-27 | 1 | -38/+50 |
| * | [NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler model | Roman Lebedev | 2018-10-27 | 1 | -0/+93 |

