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* [WebAssembly] Allow multivalue types in block signature operandsThomas Lively2019-10-152-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Renames `ExprType` to the more apt `BlockType` and adds a variant for multivalue blocks. Currently non-void blocks are only generated at the end of functions where the block return type needs to agree with the function return type, and that remains true for multivalue blocks. That invariant means that the actual signature does not need to be stored in the block signature `MachineOperand` because it can be inferred by `WebAssemblyMCInstLower` from the return type of the parent function. `WebAssemblyMCInstLower` continues to lower block signature operands to immediates when possible but lowers multivalue signatures to function type symbols. The AsmParser and Disassembler are updated to handle multivalue block types as well. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68889 llvm-svn: 374933
* [X86] Teach X86MCodeEmitter to properly encode zmm16-zmm31 as index register ↵Craig Topper2019-10-141-10/+10
| | | | | | | | | | | | to vgatherpf/vscatterpf. We need to encode bit 4 into the EVEX.V' bit. We do this right for regular gather/scatter which use either MRMSrcMem or MRMDestMem formats. The prefetches use MRM*m formats. Fixes an issue recently added to PR36202. llvm-svn: 374849
* [X86] Add encoding tests for avx512pf vgatherpf/vscatterpf instructions.Craig Topper2019-10-141-0/+65
| | | | llvm-svn: 374848
* [ARM][AsmParser] handles offset expression in parenthesesJian Cai2019-10-141-0/+20
| | | | | | | | | | | | | | | Summary: Integrated assembler does not accept offset expressions surrounded by parenthesis. Handle this case for GAS compability. https://bugs.llvm.org/show_bug.cgi?id=43631 Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68764 llvm-svn: 374832
* Revert r374652: "[lit] Fix internal diff's --strip-trailing-cr and use it"Joel E. Denny2019-10-121-1/+1
| | | | | | This series of patches still breaks a Windows bot. llvm-svn: 374679
* Revert r374653: "[lit] Fix a few oversights in r374651 that broke some bots"Joel E. Denny2019-10-121-1/+1
| | | | | | This series of patches still breaks a Windows bot. llvm-svn: 374678
* [lit] Fix a few oversights in r374651 that broke some botsJoel E. Denny2019-10-121-1/+1
| | | | llvm-svn: 374653
* [lit] Fix internal diff's --strip-trailing-cr and use itJoel E. Denny2019-10-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Using GNU diff, `--strip-trailing-cr` removes a `\r` appearing before a `\n` at the end of a line. Without this patch, lit's internal diff only removes `\r` if it appears as the last character. That seems useless. This patch fixes that. This patch also adds `--strip-trailing-cr` to some tests that fail on Windows bots when D68664 is applied. Based on what I see in the bot logs, I think the following is happening. In each test there, lit diff is comparing a file with `\r\n` line endings to a file with `\n` line endings. Without D68664, lit diff reads those files with Python's universal newlines support activated, causing `\r` to be dropped. However, with D68664, lit diff reads the files in binary mode instead and thus reports that every line is different, just as GNU diff does (at least under Ubuntu). Adding `--strip-trailing-cr` to those tests restores the previous behavior while permitting the behavior of lit diff to be more like GNU diff. Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D68839 llvm-svn: 374652
* [mips] Fix `loadImmediate` calls when load non-address values.Simon Atanasyan2019-10-121-2/+2
| | | | llvm-svn: 374640
* [mips] Store 64-bit `li.d' operand as a single 8-byte valueSimon Atanasyan2019-10-111-65/+65
| | | | | | | | | | | | | | | Now assembler generates two consecutive `.4byte` directives to store 64-bit `li.d' operand. The first directive stores high 4-byte of the value. The second directive stores low 4-byte of the value. But on 64-bit system we load this value at once and get wrong result if the system is little-endian. This patch fixes the bug. It stores the `li.d' operand as a single 8-byte value. Differential Revision: https://reviews.llvm.org/D68778 llvm-svn: 374598
* [mips] Use less instruction to load zero into FPR by li.s / li.d pseudosSimon Atanasyan2019-10-112-16/+8
| | | | | | | | | | If `li.s` or `li.d` loads zero into a FPR, it's not necessary to load zero into `at` GPR register and then move its value into a floating point register. We can use as a source register the `zero / $0` one. Differential Revision: https://reviews.llvm.org/D68777 llvm-svn: 374597
* [AMDGPU][MC][GFX9][GFX10] Corrected number of src operands for ↵Dmitry Preobrazhensky2019-10-114-58/+58
| | | | | | | | | | | | ds_[read/write]_addtid_b32 See https://bugs.llvm.org/show_bug.cgi?id=37941 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D68787 llvm-svn: 374561
* [AMDGPU][MC][GFX6][GFX7][GFX10] Added instructions ↵Dmitry Preobrazhensky2019-10-113-0/+123
| | | | | | | | | | | | buffer_atomic_[fcmpswap/fmin/fmax]* See https://bugs.llvm.org/show_bug.cgi?id=28232 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D68788 llvm-svn: 374559
* [AMDGPU][MC][GFX10] Enabled null for 64-bit dst operandsDmitry Preobrazhensky2019-10-114-1/+26
| | | | | | | | | | See https://bugs.llvm.org/show_bug.cgi?id=43524 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D68785 llvm-svn: 374557
* [AMDGPU][MC] Corrected parsing of optional operandsDmitry Preobrazhensky2019-10-111-0/+5
| | | | | | | | | | See https://bugs.llvm.org/show_bug.cgi?id=43486 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D68350 llvm-svn: 374553
* [mips] Follow-up to r374544. Fix test case.Simon Atanasyan2019-10-111-2/+2
| | | | llvm-svn: 374548
* [mips] Fix loading "double" immediate into a GPR and FPRSimon Atanasyan2019-10-111-12/+22
| | | | | | | | | | | | | | | If a "double" (64-bit) value has zero low 32-bits, it's possible to load such value into a GP/FP registers as an instruction immediate. But now assembler loads only high 32-bits of the value. For example, if a target register is GPR the `li.d $4, 1.0` instruction converts into the `lui $4, 16368` one. As a result, we get `0x3FF00000` in the register. While a correct representation of the `1.0` value is `0x3FF0000000000000`. The patch fixes that. Differential Revision: https://reviews.llvm.org/D68776 llvm-svn: 374544
* [WebAssembly] v8x16.swizzle and rewrite BUILD_VECTOR loweringThomas Lively2019-10-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Adds the new v8x16.swizzle SIMD instruction as specified at https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#swizzling-using-variable-indices. In addition to adding swizzles as a candidate lowering in LowerBUILD_VECTOR, also rewrites and simplifies the lowering to minimize the number of replace_lanes necessary rather than trying to minimize code size. This leads to more uses of v128.const instead of splats, which is expected to increase performance. The new code will be easier to tune once V8 implements all the vector construction operations, and it will also be easier to add new candidate instructions in the future if necessary. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68527 llvm-svn: 374188
* [IA] Add tests for a few other edge casesBill Wendling2019-10-081-0/+4
| | | | | | | Test with the last eight bits within the range [7F, FF] and with lower-case hex letters. llvm-svn: 374124
* [IA] Recognize hexadecimal escape sequencesBill Wendling2019-10-081-0/+5
| | | | | | | | | | | | | | | | | Summary: Implement support for hexadecimal escape sequences to match how GNU 'as' handles them. I.e., read all hexadecimal characters and truncate to the lower 16 bits. Reviewers: nickdesaulniers, jcai19 Subscribers: llvm-commits, hiraditya Tags: #llvm Differential Revision: https://reviews.llvm.org/D68598 llvm-svn: 374018
* [Mips] Fix evaluating J-format branch targetsSimon Atanasyan2019-10-072-0/+34
| | | | | | | | | | | | J/JAL/JALX/JALS are absolute branches, but stay within the current 256 MB-aligned region, so we must include the high bits of the instruction address when calculating the branch target. Patch by James Clarke. Differential Revision: https://reviews.llvm.org/D68548 llvm-svn: 373906
* Revert r373888 "[IA] Recognize hexadecimal escape sequences"Nico Weber2019-10-071-5/+0
| | | | | | | | | It broke MC/AsmParser/directive_ascii.s on all bots: Assertion failed: (Index < Length && "Invalid index!"), function operator[], file ../../llvm/include/llvm/ADT/StringRef.h, line 243. llvm-svn: 373898
* [IA] Recognize hexadecimal escape sequencesBill Wendling2019-10-071-0/+5
| | | | | | | | | | | | | | | | | Summary: Implement support for hexadecimal escape sequences to match how GNU 'as' handles them. I.e., read all hexadecimal characters and truncate to the lower 16 bits. Reviewers: nickdesaulniers Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68483 llvm-svn: 373888
* [AMDGPU][MC][GFX10][WS32] Corrected decoding of dst operand for v_cmp_*_sdwa ↵Dmitry Preobrazhensky2019-10-041-0/+6
| | | | | | | | | | | | opcodes See bug 43484: https://bugs.llvm.org/show_bug.cgi?id=43484 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D68349 llvm-svn: 373745
* [AMDGPU][MC][GFX10] Enabled decoding of 'null' operandDmitry Preobrazhensky2019-10-041-0/+7
| | | | | | | | | | See bug 43485: https://bugs.llvm.org/show_bug.cgi?id=43485 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D68348 llvm-svn: 373740
* [AMDGPU][MC][GFX10] Corrected definition of FLAT GLOBAL/SCRATCH instructionsDmitry Preobrazhensky2019-10-042-0/+95
| | | | | | | | | | See bug 43483: https://bugs.llvm.org/show_bug.cgi?id=43483 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D68347 llvm-svn: 373736
* [llvm-objdump] Further rearrange llvm-objdump sections for compatabilityJordan Rupprecht2019-10-031-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: rL371826 rearranged some output from llvm-objdump for GNU objdump compatability, but there still seem to be some more. I think this rearrangement is a little closer. Overview of the ordering which matches GNU objdump: * Archive headers * File headers * Section headers * Symbol table * Dwarf debugging * Relocations (if `--disassemble` is not used) * Section contents * Disassembly Reviewers: jhenderson, justice_adams, grimar, ychen, espindola Reviewed By: jhenderson Subscribers: aprantl, emaste, arichardson, jrtc27, atanasyan, seiya, llvm-commits, MaskRay Tags: #llvm Differential Revision: https://reviews.llvm.org/D68066 llvm-svn: 373671
* [AArch64InstPrinter] prefer bfi to bfc for < armv8.2-aNick Desaulniers2019-10-033-8/+22
| | | | | | | | | | | | | | | | | | | Summary: Fixes pr/42576. Link: https://github.com/ClangBuiltLinux/linux/issues/697 Reviewers: t.p.northover Reviewed By: t.p.northover Subscribers: kristof.beyls, hiraditya, llvm-commits, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D68356 llvm-svn: 373655
* [RISCV] Add obsolete aliases of fscsr, frcsr (fssr, frsr)Edward Jones2019-10-031-0/+12
| | | | | | | | These old aliases were renamed, but are still used by some projects (eg newlib). Differential Revision: https://reviews.llvm.org/D68392 llvm-svn: 373618
* [mips] Push `fixup_Mips_LO16` fixup for `jialc` and `jic` instructionsSimon Atanasyan2019-10-033-0/+30
| | | | llvm-svn: 373591
* [mips] Use llvm-readobj `-A` flag in test cases. NFCSimon Atanasyan2019-10-0314-17/+17
| | | | llvm-svn: 373589
* Revert "[MC] Emit unused undefined symbol even if its binding is not set"Nico Weber2019-09-302-31/+0
| | | | | | This reverts r373168. It caused PR43511. llvm-svn: 373242
* [test] Change llvm-readobj --arm-attributes to --arch-specific after r373125Fangrui Song2019-09-3033-33/+33
| | | | llvm-svn: 373179
* [MC] Emit unused undefined symbol even if its binding is not setFangrui Song2019-09-292-0/+31
| | | | | | | | | | | | | | | | | | | | | | | For the following two cases, we currently suppress the symbols. This patch emits them (compatible with GNU as). * `test2_a = undef`: if `undef` is otherwise unused. * `.hidden hidden`: if `hidden` is unused. This is the main point of the patch, because omitting the symbol would cause a linker semantic difference. It causes a behavior change that is not compatible with GNU as: .weakref foo1, bar1 When neither foo1 nor bar1 is used, we now emit bar1, which is arguably more consistent. Another change is that we will emit .TOC. for .TOC.@tocbase . For this directive, suppressing .TOC. can be seen as a size optimization, but we choose to drop it for simplicity and consistency. llvm-svn: 373168
* [AMDGPU][MC] Corrected parsing of registersDmitry Preobrazhensky2019-09-271-0/+9
| | | | | | | | | | | | | Summary of changes: refactored code for better readability and future improvements; fixed bug 41281: https://bugs.llvm.org/show_bug.cgi?id=41281 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D65224 llvm-svn: 373094
* [MC][ARM] vscclrm disassembles as vldmiaAlexandros Lamprineas2019-09-272-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Happens only when the mve.fp subtarget feature is enabled: $ llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp,+8msecext -disassemble <<< "0x9f,0xec,0x08,0x0b" .text vldmia pc, {d0, d1, d2, d3} $ llvm-mc -triple thumbv8.1m.main -mattr=+8msecext -disassemble <<< "0x9f,0xec,0x08,0x0b" .text vscclrm {d0, d1, d2, d3, vpr} Assembling returns the correct encoding with or without mve.fp: $ llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp,+8msecext -show-encoding <<< "vscclrm {d0-d3, vpr}" .text vscclrm {d0, d1, d2, d3, vpr} @ encoding: [0x9f,0xec,0x08,0x0b] $ llvm-mc -triple thumbv8.1m.main -mattr=+8msecext -show-encoding <<< "vscclrm {d0-d3, vpr}" .text vscclrm {d0, d1, d2, d3, vpr} @ encoding: [0x9f,0xec,0x08,0x0b] The problem seems to be in the TableGen description of VSCCLRMD. The least significant bit should be set to zero. Differential Revision: https://reviews.llvm.org/D68025 llvm-svn: 373052
* [WebAssembly] v128.andnotThomas Lively2019-09-271-0/+3
| | | | | | | | | | | | | | | | Summary: As specified at https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#bitwise-and-not Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68113 llvm-svn: 373041
* [WebAssembly] SIMD Load and extend operationsThomas Lively2019-09-271-0/+18
| | | | | | | | | | | | | | | | | | Summary: As specified at https://github.com/webassembly/simd/blob/master/proposals/simd/SIMD.md#load-and-extend. These instructions are behind the unimplemented-simd128 target feature for now because they have not been implemented in V8 yet. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68058 llvm-svn: 373040
* [MC][WebAssembly] Error on data symbols in the text section.Sam Clegg2019-09-251-0/+13
| | | | | | | | | Previously we had an assert but this can actually occur in valid user code so we need to handle this in release builds too. Differential Revision: https://reviews.llvm.org/D67997 llvm-svn: 372934
* [WebAssembly] vNxM.load_splat instructionsThomas Lively2019-09-231-0/+12
| | | | | | | | | | | | | | | | | | | | | | Summary: Adds the new load_splat instructions as specified at https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#load-and-splat. DAGISel does not allow matching multiple copies of the same load in a single pattern, so we use a new node in WebAssemblyISD to wrap loads that should be splatted. Depends on D67783. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67784 llvm-svn: 372655
* [AMDGPU][MC] Corrected handling of relocatable expressionsDmitry Preobrazhensky2019-09-232-1/+42
| | | | | | | | | | See bug 43359: https://bugs.llvm.org//show_bug.cgi?id=43359 Reviewers: rampitec Differential Revision: https://reviews.llvm.org/D67829 llvm-svn: 372622
* [SystemZ] Support z15 processor nameUlrich Weigand2019-09-203-4/+8
| | | | | | | | | | | The recently announced IBM z15 processor implements the architecture already supported as "arch13" in LLVM. This patch adds support for "z15" as an alternate architecture name for arch13. The patch also uses z15 in a number of places where we used arch13 as long as the official name was not yet announced. llvm-svn: 372435
* [mips] Expand 'lw/sw' instructions for 32-bit GOTSimon Atanasyan2019-09-182-2/+134
| | | | | | | | | | In case of using 32-bit GOT access to the table requires two instructions with attached %got_hi and %got_lo relocations. This patch implements correct expansion of 'lw/sw' instructions in that case. Differential Revision: https://reviews.llvm.org/D67705 llvm-svn: 372251
* [mips] Mark tests for lw/sw expansion in PIC by a separate "check prefix". NFCSimon Atanasyan2019-09-182-73/+74
| | | | | | That simplify adding XGOT tests later. llvm-svn: 372219
* [ARM] VFPv2 only supports 16 D registers.Eli Friedman2019-09-171-8/+8
| | | | | | | | | | | | | | | | | | | | r361845 changed the way we handle "D16" vs. "D32" targets; there used to be a negative "d16" which removed instructions from the instruction set, and now there's a "d32" feature which adds instructions to the instruction set. This is good, but there was an oversight in the implementation: the behavior of VFPv2 was changed. In particular, the "vfp2" feature was changed to imply "d32". This is wrong: VFPv2 only supports 16 D registers. In practice, this means if you specify -mfpu=vfpv2, the compiler will generate illegal instructions. This patch gets rid of "vfp2d16" and "vfp2d16sp", and fixes "vfp2" and "vfp2sp" so they don't imply "d32". Differential Revision: https://reviews.llvm.org/D67375 llvm-svn: 372186
* [WebAssembly] Narrowing and widening SIMD opsThomas Lively2019-09-131-0/+36
| | | | | | | | | | | | | | | | Summary: Implements target-specific LLVM intrinsics and clang builtins for these new SIMD operations, as described at https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#integer-to-integer-narrowing. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D67425 llvm-svn: 371906
* AArch64: support arm64_32, an ILP32 slice for watchOS.Tim Northover2019-09-121-0/+15
| | | | | | | | This is the main CodeGen patch to support the arm64_32 watchOS ABI in LLVM. FastISel is mostly disabled for now since it would generate incorrect code for ILP32. llvm-svn: 371722
* [RISCV] Support llvm-objdump -M no-aliases and -M numericSam Elliott2019-09-1052-76/+76
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Now that llvm-objdump allows target-specific options, we match the `no-aliases` and `numeric` options for RISC-V, as supported by GNU objdump. This is done by overriding the variables used for the command-line options, so that the command-line options are still supported. This patch updates all tests using `llvm-objdump -riscv-no-aliases` to use `llvm-objdump -M no-aliases`. Reviewers: luismarques, asb Reviewed By: luismarques, asb Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66139 llvm-svn: 371534
* [RISCV] Add Option for Printing Architectural Register NamesSam Elliott2019-09-103-0/+497
| | | | | | | | | | | | | | | | | | | | | | Summary: This is an option primarily to use during testing. Instead of always printing registers using their ABI names, this allows a user to request they are printed with their architectural name. This is then used in the register constraint tests to ensure the mapping between architectural and abi names is correct. Reviewers: asb, luismarques Reviewed By: asb Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65950 llvm-svn: 371531
* Remove some unnecessary REQUIRES: shell linesReid Kleckner2019-09-102-15/+16
| | | | | | | This means these tests will run on Windows. Replace one with UNSUPPORTED: system-windows. llvm-svn: 371473
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