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* [X86][MS-compatability]Allow named synonymous for MS-assembly operatorsCoby Tayree2017-04-041-7/+41
| | | | | | | | | | This patch enhances X86AsmParser's immediate expression parsing abilities, to include a named synonymous for selected binary/unary bitwise operators: {and,shl,shr,or,xor,not}, ultimately achieving better MS-compatability MASM reference: https://msdn.microsoft.com/en-us/library/94b6khh4.aspx Differential Revision: D31277 llvm-svn: 299439
* Reland r298901 with modifications (reverted in r298932)Weiming Zhao2017-04-0312-18/+82
| | | | | | | | | | | | | | | | | | | Dont emit Mapping symbols for sections that contain only data. Summary: Dont emit mapping symbols for sections that contain only data. Reviewers: rengolin, weimingz, kparzysz, t.p.northover, peter.smith Reviewed By: t.p.northover Patched by Shankar Easwaran <shankare@codeaurora.org> Subscribers: alekseyshl, t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D30724 llvm-svn: 299392
* ARMAsmParser: clean up of isImmediate functionsSjoerd Meijer2017-04-039-44/+54
| | | | | | | | | | | | | | | | | - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
* Revert "Dont emit Mapping symbols for sections that contain only data."Weiming Zhao2017-03-2812-82/+18
| | | | | | | | It breaks some lld tests. This reverts commit 3a50eea6d9732ab40e9a7aebe6be777b53a8b35c. llvm-svn: 298932
* [AArch64] [Assembler] option to disable negative immediate conversionsSanne Wouda2017-03-282-0/+30
| | | | | | | | | | | | | | | | | Summary: Similar to the ARM target in https://reviews.llvm.org/rL298380, this patch adds identical infrastructure for disabling negative immediate conversions, and converts the existing aliases to the new infrastucture. Reviewers: rengolin, javed.absar, olista01, SjoerdMeijer, samparker Reviewed By: samparker Subscribers: samparker, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D31243 llvm-svn: 298908
* Dont emit Mapping symbols for sections that contain only data.Weiming Zhao2017-03-2812-18/+82
| | | | | | | | | | | | | | | | | Summary: Dont emit mapping symbols for sections that contain only data. Patched by Shankar Easwaran <shankare@codeaurora.org> Reviewers: rengolin, peter.smith, weimingz, kparzysz, t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D30724 llvm-svn: 298901
* [AMDGPU][MC] Fix for Bug 28207 + LIT testsDmitry Preobrazhensky2017-03-271-1/+131
| | | | | | | | | | Enabled clamp and omod for v_cvt_* opcodes which have src0 of an integer type Reviewers: vpykhtin, arsenm Differential Revision: https://reviews.llvm.org/D31327 llvm-svn: 298852
* [AMDGPU] Rename Kind to ValueKind in metadata to be consistentKonstantin Zhuravlyov2017-03-242-15/+15
| | | | llvm-svn: 298722
* [Mips] Fix for decoding DINS instruction - disassemblerStrahinja Petrovic2017-03-231-1/+1
| | | | | | | | | This patch fixes decoding of size and position for DINSM and DINSU instructions. Differential Revision: https://reviews.llvm.org/D31072 llvm-svn: 298593
* [AMDGPU] Do not emit isa info as code object metadataKonstantin Zhuravlyov2017-03-224-146/+0
| | | | | | | | - It was decided to expose this information through other means (rocr) Differential Revision: https://reviews.llvm.org/D30970 llvm-svn: 298560
* [AMDGPU] Emit kernel debug properties as code object metadataKonstantin Zhuravlyov2017-03-222-4/+30
| | | | | | Differential Revision: https://reviews.llvm.org/D30969 llvm-svn: 298558
* [AMDGPU] Emit kernel code properties as code object metadataKonstantin Zhuravlyov2017-03-221-0/+24
| | | | | | | | - These are not required for low level runtime Differential Revision: https://reviews.llvm.org/D29949 llvm-svn: 298556
* [AMDGPU] Restructure code object metadata creationKonstantin Zhuravlyov2017-03-228-202/+295
| | | | | | | | | | | | | | | | | - Rename runtime metadata -> code object metadata - Make metadata not flow - Switch enums to use ScalarEnumerationTraits - Cleanup and move AMDGPUCodeObjectMetadata.h to AMDGPU/MCTargetDesc - Introduce in-memory representation for attributes - Code object metadata streamer - Create metadata for isa and printf during EmitStartOfAsmFile - Create metadata for kernel during EmitFunctionBodyStart - Finalize and emit metadata to .note during EmitEndOfAsmFile - Other minor improvements/bug fixes Differential Revision: https://reviews.llvm.org/D29948 llvm-svn: 298552
* Add default typo to .tbss.*Rafael Espindola2017-03-221-0/+8
| | | | | | This matches gas behavior and is part of pr31888. llvm-svn: 298508
* Set the default type for .bss.foo.Rafael Espindola2017-03-221-0/+8
| | | | | | This matches gas and is part of pr31888. llvm-svn: 298506
* Produce INIT_ARRAY for sections named .init_array.*Rafael Espindola2017-03-221-0/+4
| | | | | | | These sections are merged together by the linker, so they should have the same time. llvm-svn: 298505
* [AMDGPU][MC] Fix for Bug 28204 + LIT testsDmitry Preobrazhensky2017-03-221-0/+10
| | | | | | | | | | Fixed v_mad_i64_i32/u64_u32 encoding Reviewers: artem.tamazov Differential Revision: https://reviews.llvm.org/D30828 llvm-svn: 298502
* [ARM] [Assembler] Support negative immediates for A32, T32 and T16Sanne Wouda2017-03-214-0/+175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
* [AMDGPU][MC] Fix for Bugs 28201, 28199, 28170 + LIT testsDmitry Preobrazhensky2017-03-201-0/+12
| | | | | | | | | | This fix enables sp3 abs modifier with constants Reviewers: artem.tamazov Differential Revision: https://reviews.llvm.org/D30825 llvm-svn: 298265
* [AMDGPU][MC] Fix for Bugs 28200, 28202 + LIT testsDmitry Preobrazhensky2017-03-205-6/+285
| | | | | | | | | | Fixed several related issues with VOP3 fp modifiers. Reviewers: artem.tamazov Differential Revision: https://reviews.llvm.org/D30821 llvm-svn: 298255
* [Asm] Don't list '@<type>' in diag when '@' is a commentOliver Stannard2017-03-171-0/+4
| | | | | | | | This fixes https://bugs.llvm.org//show_bug.cgi?id=31280 Differential revision: https://reviews.llvm.org/D31026 llvm-svn: 298067
* [ARM] Fix triple format in test branch disassemble testAndre Vieira2017-03-172-7/+22
| | | | | | | | | | | | Fixing triple format in the tests added for the branch label fix for Thumb Targets. Also recommitting previously approved patch, see https://reviews.llvm.org/D30943. Reviewed by: samparker Differential Revision: https://reviews.llvm.org/D30987 llvm-svn: 298056
* [Hexagon] Fixing test from 297920 to add Hexagon triple.Colin LeMahieu2017-03-161-2/+2
| | | | llvm-svn: 297926
* Check that line table entries don't spill over between sections even if ↵David Blaikie2017-03-161-0/+15
| | | | | | they're empty at the end of a section llvm-svn: 297922
* [Hexagon] Updating inline saturate lanes for v62 version.Colin LeMahieu2017-03-161-0/+13
| | | | llvm-svn: 297920
* [PowerPC][Altivec] Add mfvrd and mffprd extended mnemonicNemanja Ivanovic2017-03-152-5/+8
| | | | | | | | | | | mfvrd and mffprd are both alias to mfvrsd. This patch enables correct parsing of the aliases, but we still emit a mfvrsd. Committing on behalf of brunoalr (Bruno Rosa). Differential Revision: https://reviews.llvm.org/D29177 llvm-svn: 297849
* Reverting r297821 due to breaking lld test.Sam Parker2017-03-152-64/+49
| | | | llvm-svn: 297838
* [Mips] Add support to match more patterns for DEXT and CINSPetar Jovanovic2017-03-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for recognizing more patterns to match to DEXT and CINS instructions. It finds cases where multiple instructions could be replaced with a single DEXT or CINS instruction. For example, for the following: define i64 @dext_and32(i64 zeroext %a) { entry: %and = and i64 %a, 4294967295 ret i64 %and } instead of generating: 0000000000000088 <dext_and32>: 88: 64010001 daddiu at,zero,1 8c: 0001083c dsll32 at,at,0x0 90: 6421ffff daddiu at,at,-1 94: 03e00008 jr ra 98: 00811024 and v0,a0,at 9c: 00000000 nop the following gets generated: 0000000000000068 <dext_and32>: 68: 03e00008 jr ra 6c: 7c82f803 dext v0,a0,0x0,0x20 Cases that are covered: DEXT: 1. and $src, mask where mask > 0xffff 2. zext $src zero extend from i32 to i64 CINS: 1. and (shl $src, pos), mask 2. shl (and $src, mask), pos 3. zext (shl $src, pos) zero extend from i32 to i64 Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D30464 llvm-svn: 297832
* [ARM] Fix for branch label disassembly for ThumbSam Parker2017-03-152-49/+64
| | | | | | | | | | | | | | | | | Different MCInstrAnalysis classes for arm and thumb mode, each with their own evaluateBranch implementation. I added a test case and fixed the coff-relocations test to use '<label>:' rather than '<label>' in the CHECK-LABEL entries, since the ones without the colon would match branch targets. Might be worth noticing that llvm-objdump does not lookup the relocation and thus assigns it a target depending on the encoded immediate which #0, so it thinks it branches to the next instruction. Committed on behalf of Andre Vieira (avieira). Differential Revision: https://reviews.llvm.org/D30943 llvm-svn: 297821
* Fix asm printing of associated sections.Evgeniy Stepanov2017-03-141-0/+4
| | | | | | | Make MCSectionELF::AssociatedSection be a link to a symbol, because that's how it works in the assembly, and use it in the asm printer. llvm-svn: 297769
* [ARM] Diagnose ARM MOVT without :lower16: or :upper16: expressionOliver Stannard2017-03-141-0/+3
| | | | | | | | | | | This instruction was missing from the list of opcodes that we check, so we were hitting an llvm_unreachable in ARMMCCodeEmitter.cpp for the ARM MOVT instruction, rather than the diagnostic that is emitted for the other MOVW/MOVT instructions. Differential revision: https://reviews.llvm.org/D30936 llvm-svn: 297739
* [Assembler] Add location info to unary expressions.Sanne Wouda2017-03-102-2/+2
| | | | | | | | | | | | | | | | | Summary: This is a continuation of D28861. Add an SMLoc to MCUnaryExpr such that a better diagnostic can be given in case of an error in later stages of assembling. Reviewers: rengolin, grosbach, javed.absar, olista01 Reviewed By: olista01 Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30581 llvm-svn: 297454
* [llvm-readobj] Support SHT_MIPS_DWARF section type flagSimon Atanasyan2017-03-101-0/+6
| | | | llvm-svn: 297448
* [MC] Accept a numeric value as an ELF section header's typeSimon Atanasyan2017-03-102-0/+34
| | | | | | | | | | | | | | | | | | | | | | GAS supports specification of section header's type using a numeric value [1]. This patch brings the same functionality to LLVM. That allows to setup some target-specific section types belong to the SHT_LOPROC - SHT_HIPROC range. If we attempt to print unknown section type, MCSectionELF class shows an error message. It's better than print sole '@' sign without any section type name. In case of MIPS, example of such section's type is SHT_MIPS_DWARF. Without the patch we will have to implement some workarounds in probably not-MIPS-specific part of code base to convert SHT_MIPS_DWARF to the @progbits while printing assembly and to assign SHT_MIPS_DWARF for @progbits sections named .debug_* if we encounter such section in an input assembly. [1] https://sourceware.org/binutils/docs/as/Section.html Differential Revision: https://reviews.llvm.org/D29719 llvm-svn: 297446
* [ARM] Remove t2xtpk feature from testsSam Parker2017-03-091-2/+2
| | | | | | | | | I previously removed the T2XtPk feature from the ARM backend, but it looks like I missed some of the tests that were using the feature. Differential Revision: https://reviews.llvm.org/D30778 llvm-svn: 297386
* [ARM] remove FIXMEs and add vcmp MC testSjoerd Meijer2017-03-091-0/+12
| | | | | | | | | Minor cleanup in ARMInstrVFP.td: removed some FIXMEs and added a MC test for vcmp that was actually missing. Differential Revision: https://reviews.llvm.org/D30745 llvm-svn: 297376
* [ARM] Split up lsl-zero test into two testsJohn Brawn2017-03-082-99/+105
| | | | | | | | On Windows stderr and stdout happen to get interleaved in a way that causes the test to fail, so split it up into a test that checks for errors and a test that doesn't. llvm-svn: 297273
* [ARM] Correct handling of LSL #0 in an IT blockJohn Brawn2017-03-071-0/+14
| | | | | | | | | | | The check for LSL #0 in an IT block was checking if operand 4 was zero, but operand 4 is the condition code operand so it was actually checking for LSLEQ. Fix this by checking operand 3, which really is the immediate operand, and add some tests. Differential Revision: https://reviews.llvm.org/D30692 llvm-svn: 297142
* [AMDGPU][MC] Fix for Bug 30829 + LIT testsDmitry Preobrazhensky2017-03-032-0/+297
| | | | | | | | Added code to check constant bus restrictions for VOP formats (only one SGPR value or literal-constant may be used by the instruction). Note that the same checks are performed by SIInstrInfo::verifyInstruction (used by lowering code). Added LIT tests. llvm-svn: 296873
* [Hexagon] Fix testcase accidentally broken by r296645Krzysztof Parzyszek2017-03-011-2/+2
| | | | llvm-svn: 296647
* [ARM] Fix bash-ism in testOliver Stannard2017-03-011-2/+2
| | | | llvm-svn: 296610
* [ARM] Fix parsing of special register masksOliver Stannard2017-03-011-0/+11
| | | | | | | | | | | | This parsing code was incorrectly checking for invalid characters, so an invalid instruction like: msr spsr_w, r0 would be emitted as: msr spsr_cxsf, r0 Differential revision: https://reviews.llvm.org/D30462 llvm-svn: 296607
* [DWARFv5] llvm-mc support for new unit header.Paul Robinson2017-02-282-17/+32
| | | | | | | | | This is for running the assembler with -g (to emit DWARF describing the assembler source). Differential Revision: http://reviews.llvm.org/D30475 llvm-svn: 296541
* AMDGPU: Add definition for v_swap_b32Matt Arsenault2017-02-283-0/+42
| | | | | | | | This is somewhat tricky because there are two pairs of tied operands, and it isn't allowed to be VOP3 encoded. llvm-svn: 296519
* AMDGPU: Add definition for v_xad_u32Matt Arsenault2017-02-281-0/+4
| | | | llvm-svn: 296515
* AMDGPU: Add ds_nop to assemblerMatt Arsenault2017-02-281-0/+5
| | | | llvm-svn: 296513
* AMDGPU: Add definitions for ds_{read|write}_b{96|128}Matt Arsenault2017-02-281-0/+9
| | | | | | | | | It's not clear to me if this is always better than doing ds_write2_b64 This adds the constraint of a 128-bit register input instead of a pair of 64-bit. llvm-svn: 296512
* [AMDGPU] Change amd_kernel_code_t's minor version to 1Konstantin Zhuravlyov2017-02-282-2/+2
| | | | | | | | - We do emit amd_kernel_code_t v1.1 Differential Revision: https://reviews.llvm.org/D30433 llvm-svn: 296489
* [mips] Fix 64bit slt/sltu/nor with immediatesSimon Dardis2017-02-282-106/+326
| | | | | | | | | | Patch By: Alexander Richardson Reviewers: atanasyan, theraven, sdardis Differential Revision: https://reviews.llvm.org/D30330 llvm-svn: 296482
* [Assembler] Add test for !srcloc references in assembler diagsSanne Wouda2017-02-281-0/+37
| | | | | | | | | | | | | | | | | | | | | | | Summary: clang adds !srcloc metadata to inline assembly in LLVM bitcode generated for inline assembly in C. The value of this !srcloc is passed to the diagnostics handler if the inline assembly generates a diagnostic. clang is able to turn this cookie back to a location in the C source file. To test this functionality without a dependency, make llc print the !srcloc metadata if it is present. The added test uses this mechanism to test that the correct !srclocs are passed to the diag handler. Reviewers: rengolin, rnk, echristo, grosbach, mehdi_amini Reviewed By: mehdi_amini Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D30167 llvm-svn: 296465
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