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| author | Coby Tayree <coby.tayree@intel.com> | 2017-04-04 14:43:23 +0000 |
|---|---|---|
| committer | Coby Tayree <coby.tayree@intel.com> | 2017-04-04 14:43:23 +0000 |
| commit | 2cb497afa46a0c6fe8ed6c5793e59d9e0b054a68 (patch) | |
| tree | f62568e7f0bb57aa0b592321842866218f81f38e /llvm/test/MC | |
| parent | 448222d8bad122e857df2356ae15b2a5c12b2590 (diff) | |
| download | bcm5719-llvm-2cb497afa46a0c6fe8ed6c5793e59d9e0b054a68.tar.gz bcm5719-llvm-2cb497afa46a0c6fe8ed6c5793e59d9e0b054a68.zip | |
[X86][MS-compatability]Allow named synonymous for MS-assembly operators
This patch enhances X86AsmParser's immediate expression parsing abilities, to include a named synonymous for selected binary/unary bitwise operators: {and,shl,shr,or,xor,not}, ultimately achieving better MS-compatability
MASM reference:
https://msdn.microsoft.com/en-us/library/94b6khh4.aspx
Differential Revision: D31277
llvm-svn: 299439
Diffstat (limited to 'llvm/test/MC')
| -rw-r--r-- | llvm/test/MC/X86/intel-syntax-bitwise-ops.s | 48 |
1 files changed, 41 insertions, 7 deletions
diff --git a/llvm/test/MC/X86/intel-syntax-bitwise-ops.s b/llvm/test/MC/X86/intel-syntax-bitwise-ops.s index 1f09996fe91..6d4df609c06 100644 --- a/llvm/test/MC/X86/intel-syntax-bitwise-ops.s +++ b/llvm/test/MC/X86/intel-syntax-bitwise-ops.s @@ -6,19 +6,53 @@ and ecx, 1+2 // CHECK: andl $3, %ecx and ecx, 1|2 -// CHECK: andl $3, %ecx +// CHECK: andl $3, %ecx + and ecx, 1 or 2 +// CHECK: andl $3, %ecx + and ecx, 1 OR 2 +// CHECK: andl $3, %ecx and ecx, 1*3 // CHECK: andl $1, %ecx and ecx, 1&3 -// CHECK: andl $0, %ecx +// CHECK: andl $1, %ecx + and ecx, 1 and 3 +// CHECK: andl $1, %ecx + and ecx, 1 AND 3 +// CHECK: andl $0, %ecx and ecx, (1&2) -// CHECK: andl $3, %ecx +// CHECK: andl $0, %ecx + and ecx, (1 and 2) +// CHECK: andl $0, %ecx + and ecx, (1 AND 2) +// CHECK: andl $3, %ecx and ecx, ((1)|2) -// CHECK: andl $1, %ecx +// CHECK: andl $3, %ecx + and ecx, ((1) or 2) +// CHECK: andl $3, %ecx + and ecx, ((1) OR 2) +// CHECK: andl $1, %ecx and ecx, 1&2+3 -// CHECK: addl $4938, %eax +// CHECK: andl $1, %ecx + and ecx, 1 and 2+3 +// CHECK: andl $1, %ecx + and ecx, 1 AND 2+3 +// CHECK: addl $4938, %eax add eax, 9876 >> 1 -// CHECK: addl $19752, %eax +// CHECK: addl $4938, %eax + add eax, 9876 shr 1 +// CHECK: addl $4938, %eax + add eax, 9876 SHR 1 +// CHECK: addl $19752, %eax add eax, 9876 << 1 -// CHECK: addl $5, %eax +// CHECK: addl $19752, %eax + add eax, 9876 shl 1 +// CHECK: addl $19752, %eax + add eax, 9876 SHL 1 +// CHECK: addl $5, %eax add eax, 6 ^ 3 +// CHECK: addl $5, %eax + add eax, 6 xor 3 +// CHECK: addl $5, %eax + add eax, 6 XOR 3 +// CHECK: addl $5, %eax + add eax, 6 XOR 3 shl 1 SHR 1 |
