| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | The patch adds missing registers and instructions to complete all the ↵ | Chris Dewhurst | 2016-02-27 | 1 | -11/+19 |
| | | | | | | | | | | | | | | registers supported by the Sparc v8 manual. These are all co-processor registers, with the exception of the floating-point deferred-trap queue register. Although these will not be lowered automatically by any instructions, it allows the use of co-processor instructions implemented by inline-assembly. Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td, which was formerly causing a problem in the disassembly of the %fq register. llvm-svn: 262133 | ||||
| * | Reverting breaking change. Sorry. | Chris Dewhurst | 2016-02-26 | 1 | -19/+11 |
| | | | | | llvm-svn: 262007 | ||||
| * | Reviewed at reviews.llvm.org/D17133 | Chris Dewhurst | 2016-02-26 | 1 | -11/+19 |
| | | | | | llvm-svn: 262005 | ||||
| * | Load/store instructions for floating points with address space require SparcV9. | Joerg Sonnenberger | 2015-08-18 | 1 | -22/+2 |
| | | | | | | | | | To properly handle this, define the *a instructions as separate instruction classes by refactoring the LoadA and StoreA multiclasses. Move the instruction tests into the sparcv9 file to test the difference. llvm-svn: 245360 | ||||
| * | Load/store for float registers from/to alternate space. | Joerg Sonnenberger | 2015-08-10 | 1 | -0/+29 |
| | | | | | llvm-svn: 244532 | ||||
| * | TableGen: fix operand counting for aliases | Tim Northover | 2014-05-16 | 1 | -6/+6 |
| | | | | | | | | | | | | | | | | | | | | | | TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969 | ||||
| * | [Sparc] Add fcmpe* instructions to Sparc backend. | Venkatraman Govindaraju | 2014-03-02 | 1 | -0/+14 |
| | | | | | llvm-svn: 202661 | ||||
| * | [Sparc] Add support for parsing fcmp with %fcc registers. | Venkatraman Govindaraju | 2014-03-02 | 1 | -3/+10 |
| | | | | | llvm-svn: 202610 | ||||
| * | [Sparc] Correct quad register list in the asm parser. | Venkatraman Govindaraju | 2014-01-24 | 1 | -0/+6 |
| | | | | | | | Add test cases to check parsing of v9 double registers and their aliased quad registers. llvm-svn: 199974 | ||||
| * | [Sparc] Add support for parsing floating point instructions. | Venkatraman Govindaraju | 2014-01-12 | 1 | -0/+113 |
| llvm-svn: 199033 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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