| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Add pseudo instruction for calls with explicit register | Lewis Revill | 2019-06-26 | 1 | -0/+14 |
| * | [RISCV] Support assembling @plt symbol operands | Alex Bradbury | 2019-04-02 | 1 | -0/+8 |
| * | [RISCV] Support named operands for CSR instructions. | Ana Pazos | 2018-10-04 | 1 | -0/+6 |
| * | [RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table | Shiva Chen | 2018-05-30 | 1 | -5/+5 |
| * | [RISCV] Allow call pseudoinstruction to be used to call a function name that ... | Alex Bradbury | 2018-04-25 | 1 | -0/+20 |
| * | [RISCV] Support "call" pseudoinstruction in the MC layer | Shiva Chen | 2018-04-25 | 1 | -0/+19 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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