summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC/Mips/mt
Commit message (Collapse)AuthorAgeFilesLines
* [mips] Use llvm-readobj `-A` flag in test cases. NFCSimon Atanasyan2019-10-033-3/+3
| | | | llvm-svn: 373589
* [llvm-readobj] Change -long-option to --long-option in tests. NFCFangrui Song2019-05-013-3/+3
| | | | | | | | | | We use both -long-option and --long-option in tests. Switch to --long-option for consistency. In the "llvm-readelf" mode, -long-option is discouraged as it conflicts with grouped short options and it is not accepted by GNU readelf. While updating the tests, change llvm-readobj -s to llvm-readobj -S to reduce confusion ("s" is --section-headers in llvm-readobj but --symbols in llvm-readelf). llvm-svn: 359649
* [mips][mt] Add missing test cases from r318207Simon Dardis2017-11-165-0/+100
| | | | llvm-svn: 318389
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-11-142-11/+32
| | | | | | | | | | | | | | | | | | | | This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 318207
* Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-08-147-145/+11
| | | | | | | This reverts r310834. It didn't pacify the buildbot, FileCheck is still crashing. llvm-svn: 310854
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-08-147-24/+159
| | | | | | | | | | | | | | | | | | | | This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 310834
* Revert "Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-07-148-161/+25
| | | | | | | | | FileCheck is crashing on in the input file, so reverting again while I investigate. This reverts r308023. llvm-svn: 308030
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions.""Simon Dardis2017-07-148-25/+161
| | | | | | | | | | | | | | | | | | | | | | | | Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 The last version of this patch broke one of the expensive checks buildbots, this version changes the failing test/MC/Mips/mt/invalid.s and other invalid tests to write the errors to a file and run FileCheck on that, rather than relying on the 'not llvm-mc ... <%s 2>&1 | Filecheck %s' idiom. Hopefully this will sarisfy the buildbot. llvm-svn: 308023
* Revert "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-07-137-156/+23
| | | | | | | This reverts r307836, it broke one of the buildbots. Reverting while I investigate. llvm-svn: 307939
* [mips][mt][6/7] Add support for mftr, mttr instructions.Simon Dardis2017-07-127-23/+156
| | | | | | | | | | | | | | | | | Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 307836
* [mips][mt][5/7] Add support for fork and yield instructions.Simon Dardis2017-07-121-1/+3
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35252 llvm-svn: 307808
* [mips][mt][4/7] Add IAS support for dvpe, evpe instructions.Simon Dardis2017-07-122-0/+11
| | | | | | | | Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35251 llvm-svn: 307793
* [mips][mt] Add missing files from last commitSimon Dardis2017-07-122-0/+13
| | | | llvm-svn: 307779
* [mips][mt][2/7] Implement .module and .set directives for the MT ASE.Simon Dardis2017-07-113-0/+36
| | | | | | | | | | | | This patch implements the .module and .set directives for the MT ASE, notably that .module sets the relevant flags in .MIPS.abiflags and .set doesn't. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35249 llvm-svn: 307716
* [mips][mt][1/7] Add the MT ASE as a subtarget feature.Simon Dardis2017-07-111-0/+10
Preparatory work for adding the MIPS MT (multi-threading) ASE instructions. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35247 llvm-svn: 307679
OpenPOWER on IntegriCloud