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Summary: They aren't necessary since llvm-objdump can auto-detect the architecture.
Reviewers: sdardis
Subscribers: jfb, dsanders, llvm-commits, sdardis
Differential Revision: http://reviews.llvm.org/D20904
llvm-svn: 271653
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lld tests need to be addressed.
llvm-svn: 265822
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Differential Revision: http://reviews.llvm.org/D18770
llvm-svn: 265817
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transformed to the final instruction variant. An
example would be dsrll which is transformed into
dsll32 if the shift value is greater than 32.
For direct object output we need to do this transformation
in the codegen. If the instruction was inside branch
delay slot, it was being missed. This patch corrects this
oversight.
llvm-svn: 162779
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default.
Patch by Carl Norum.
llvm-svn: 162339
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Mips shift instructions DSLL, DSRL and DSRA are transformed into
DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between
32 and 63
Here is a description of DSLL:
Purpose: Doubleword Shift Left Logical Plus 32
To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits
Description: GPR[rd] <- GPR[rt] << (sa+32)
The 64-bit doubleword contents of GPR rt are shifted left, inserting
zeros into the emptied bits; the result is placed in
GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa.
This patch implements the direct object output of these instructions.
llvm-svn: 160277
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