| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. | Daniel Sanders | 2015-06-27 | 1 | -0/+4 |
| * | [mips64] Emit correct addend for some PC-relative relocations | Petar Jovanovic | 2015-06-23 | 1 | -20/+20 |
| * | [mips] Change existing uimm10 operand to restrict the accepted immediates | Zoran Jovanovic | 2015-06-11 | 1 | -0/+4 |
| * | [mips][msa] Test basic operations for the N32 ABI too. | Daniel Sanders | 2015-05-05 | 1 | -0/+3 |
| * | [mips][mips64r6] Sorted instructions in test. NFC. | Daniel Sanders | 2015-04-30 | 1 | -96/+96 |
| * | [mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic. | Toma Tabacu | 2015-04-08 | 1 | -1/+8 |
| * | [mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction. | Toma Tabacu | 2015-03-17 | 1 | -0/+1 |
| * | Recommit "[mips] Add names and tests for the hardware registers" | Vasileios Kalintiris | 2014-11-11 | 1 | -0/+6 |
| * | Revert "[mips] Add names and tests for the hardware registers" | Rafael Espindola | 2014-11-04 | 1 | -6/+0 |
| * | [mips] Add names and tests for the hardware registers | Vasileios Kalintiris | 2014-11-04 | 1 | -0/+6 |
| * | [mips] Add support for COP1's Branch-On-Cond-Likely instructions | Vasileios Kalintiris | 2014-10-17 | 4 | -6/+6 |
| * | [mips] Add support for COP0's Branch-On-Cond-Likely instructions | Vasileios Kalintiris | 2014-10-17 | 2 | -8/+8 |
| * | [mips] Marked the DI/EI instruction aliases as MIPS32r2 | Vasileios Kalintiris | 2014-10-16 | 1 | -0/+4 |
| * | [mips] Improve the error messages given by MipsAsmParser. | Toma Tabacu | 2014-09-16 | 5 | -80/+80 |
| * | [mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to MipsIns... | Toma Tabacu | 2014-09-16 | 1 | -0/+1 |
| * | [mips] Marked the ADDi instruction aliases as not available in Mips32R6 and M... | Toma Tabacu | 2014-09-16 | 1 | -0/+4 |
| * | [mips] Marked the DADDiu instruction aliases as MIPS III. | Toma Tabacu | 2014-09-15 | 1 | -0/+4 |
| * | [mips] Marked the Trap-on-Condition instructions as Mips II | Daniel Sanders | 2014-09-05 | 1 | -0/+12 |
| * | [mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions | Daniel Sanders | 2014-07-09 | 1 | -20/+20 |
| * | [mips][mips64r6] Correct the encoding of dmuh, dmuhu, dmul, and dmulu. | Daniel Sanders | 2014-07-04 | 1 | -4/+4 |
| * | [mips] Added support for assembling sdbbp. | Daniel Sanders | 2014-06-24 | 1 | -0/+2 |
| * | ps][mips64r6] Added LSA/DLSA instructions | Zoran Jovanovic | 2014-06-20 | 1 | -0/+2 |
| * | [mips] SYNC $stype instruction was added in Mips32 | Matheus Almeida | 2014-06-18 | 1 | -0/+2 |
| * | [mips][mips64r6] Add BLTC and BLTUC instructions | Zoran Jovanovic | 2014-06-18 | 1 | -0/+2 |
| * | [mips] Implement alias for 'and' and 'or' instructions for all ISAs. | Matheus Almeida | 2014-06-18 | 1 | -0/+2 |
| * | [mips][mips64r6] ssnop is deprecated on MIPS32r6/MIPS64r6 | Daniel Sanders | 2014-06-16 | 1 | -1/+4 |
| * | [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6 | Daniel Sanders | 2014-06-16 | 1 | -0/+4 |
| * | [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. | Daniel Sanders | 2014-06-16 | 1 | -0/+4 |
| * | [mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates rat... | Daniel Sanders | 2014-06-16 | 2 | -2/+8 |
| * | [mips][mips64r6] Relocation R_MIPS_PC18_S3 | Zoran Jovanovic | 2014-06-13 | 1 | -1/+7 |
| * | [mips] Add cache and pref instructions | Daniel Sanders | 2014-06-13 | 1 | -0/+2 |
| * | [mips][mips64r6] bc1any[24] are not available on MIPS32r6/MIPS64r6 | Daniel Sanders | 2014-06-13 | 1 | -1/+5 |
| * | [mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal i... | Daniel Sanders | 2014-06-13 | 7 | -0/+19 |
| * | [mips][mips64r6] daddi is not available on MIPS64r6 | Daniel Sanders | 2014-06-13 | 1 | -1/+9 |
| * | [mips][mips64r6] bc2[ft] are not available on MIPS32r6/MIPS64r6 | Daniel Sanders | 2014-06-12 | 2 | -0/+22 |
| * | [mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 | Daniel Sanders | 2014-06-12 | 2 | -0/+20 |
| * | [mips][mips64r6] prefx is not available on MIPS32r6/MIPS64r6 | Daniel Sanders | 2014-06-12 | 1 | -0/+21 |
| * | [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available ... | Daniel Sanders | 2014-06-12 | 2 | -0/+16 |
| * | [mips][mips64r6] jalx is not available on MIPS32r6/MIPS64r6 | Daniel Sanders | 2014-06-12 | 1 | -0/+31 |
| * | [mips][mips64r6] Add R_MIPS_PC19_S2 | Zoran Jovanovic | 2014-06-12 | 1 | -6/+21 |
| * | [mips][mips64r6] Add bgec and bgeuc instructions | Zoran Jovanovic | 2014-06-12 | 1 | -0/+2 |
| * | [mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, d... | Daniel Sanders | 2014-06-12 | 4 | -1/+41 |
| * | [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register ... | Matheus Almeida | 2014-06-11 | 2 | -0/+13 |
| * | [mips][mips64r6] Add LDPC instruction | Zoran Jovanovic | 2014-06-09 | 1 | -0/+1 |
| * | [mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16 | Zoran Jovanovic | 2014-05-27 | 1 | -0/+12 |
| * | [mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 | Zoran Jovanovic | 2014-05-27 | 1 | -0/+43 |
| * | [mips][mips64r6] t(eq|ge|lt|ne)i and t(ge|lt)iu are not available in MIPS32r6... | Daniel Sanders | 2014-05-23 | 2 | -0/+20 |
| * | [mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 | Daniel Sanders | 2014-05-23 | 3 | -0/+46 |
| * | [mips][mips64r6] addi is not available on MIPS32r6/MIPS64r6 | Daniel Sanders | 2014-05-22 | 1 | -0/+8 |
| * | [mips][mips64r6] Test that paired single instructions are invalid | Daniel Sanders | 2014-05-22 | 1 | -0/+44 |
