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* [mips] Fix the predicates of round, ceiling, floor and trunc.Simon Dardis2018-05-141-6/+14
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46691 llvm-svn: 332258
* [mips] Correct the predicates of cvt.fmt.fmt instructionsSimon Dardis2018-05-101-10/+20
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46390 llvm-svn: 331969
* [mips] Correct the predicates for shifts.Simon Dardis2018-05-021-0/+30
| | | | | | | | Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
* Reland "[mips] Guard traps for microMIPS correctly"Simon Dardis2018-04-241-18/+18
| | | | | | | | | | | | | | This is part of fixing the instruction predicates for MIPS. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44212 This patch relands r327409, hopefully without the problematic part of the tests that cause FileCheck to assert on the windows expensive checks bot. llvm-svn: 330741
* [mips] Correct the predicates for special nops, tlb ctrl instrs, software ↵Simon Dardis2018-04-121-1/+9
| | | | | | | | | | breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
* Revert "[mips] Guard traps for microMIPS correctly"Simon Dardis2018-03-131-43/+7
| | | | | | | | | This appears to have broken the expensive checks bot in a strange fashion. Reverting until I can investigate. This reverts r327409. llvm-svn: 327427
* [mips] Guard traps for microMIPS correctlySimon Dardis2018-03-131-7/+43
| | | | | | | | | | This is part of fixing the instruction predicates for MIPS. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44212 llvm-svn: 327409
* [mips] Add instruction aliases for ds(r|l)l.Simon Dardis2017-06-271-0/+4
| | | | | | | Add the instruction aliases for ds(r|l)l for the two operand alias of ds(r|l)lv and the aliases ds(r|l)l with the three register operands. llvm-svn: 306405
* [mips] not instruction aliasSimon Dardis2016-11-161-0/+2
| | | | | | | | | | | This patch adds the single operand form of the not alias to microMIPS and MIPS along with additional tests. This partially resolves PR/30381. Thanks to Sean Bruno for reporting the issue! llvm-svn: 287097
* [mips] Fix sync instruction definitionSimon Dardis2016-10-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | The 'sync' instruction for MIPS was defined in MIPS-II as taking no operands. MIPS32 extended the define of 'sync' as taking an optional unsigned 5 bit immediate. This patch correct the definition of sync so that it is accepted with an operand of 0 or no operand for MIPS-II to MIPS-V, and a 5 bit unsigned immediate for MIPS32 and later revisions. Additionally a clear error is given when the MIPS32 version of sync is used when targeting pre MIPS32. This partially resolves PR/30714. Thanks to Daniel Sanders for reporting this issue! Reveiwers: vkalintiris Differential Revision: https://reviews.llvm.org/D25672 llvm-svn: 284483
* [mips] Add l.[sd] and s.[sd] instruction aliasesSimon Dardis2016-08-171-0/+4
| | | | | | | | Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23121 llvm-svn: 278930
* [mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliasesSimon Dardis2016-07-261-0/+9
| | | | | | | | | | | Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
* [mips] Correct label prefixes for N32 and N64.Daniel Sanders2016-07-191-2/+2
| | | | | | | | | | | | | | | | | Summary: N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own ($). This fixes the majority of object differences between -fintegrated-as and -fno-integrated-as. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D22412 llvm-svn: 275967
* [mips] Weaken asm predicate for memory offsetsSimon Dardis2016-05-271-0/+31
| | | | | | | | | | | | The isMemWithSimmOffset predicate rejects relocations which is incorrect behaviour. Linkers and other tools should handle|warn|error when the field overflows. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D20727 llvm-svn: 270995
* [mips] Range check uimm20 and fixed a bug this revealed.Daniel Sanders2016-02-291-0/+2
| | | | | | | | | | | | | | | | | | | Summary: The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when printing assembly. This came up when replacing MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary bit widths. MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been removed. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15521 llvm-svn: 262231
* [mips] added support for trunc macroZoran Jovanovic2016-02-221-4/+6
| | | | | | | | Author: obucina Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D15745 llvm-svn: 261529
* [mips] Never select JAL for calls to an absolute immediate address.Daniel Sanders2016-01-111-0/+1
| | | | | | | | | | | | | | | Summary: It actually takes an offset into the current PC-region. This fixes the 'expr' command in lldb. Reviewers: vkalintiris, jaydeep, bhushan Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16054 llvm-svn: 257339
* [mips] Remap move as or.Vasileios Kalintiris2015-08-111-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or 'addu'. The use of addu/daddu instead of or as move was highlighted as a performance issue during the analysis of a recent 64bit design. Originally move was encoded as 'or' by binutils but was changed for the r10k cpu family due to their pipeline which had 2 arithmetic units and a single logical unit, and so could issue multiple (d)addu based moves at the same time but only 1 logical move. This patch preserves the disassembly behaviour so that disassembling a old style (d)addu move still appears as move, but assembling move always gives an or Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11796 llvm-svn: 244579
* [mips][msa] Test basic operations for the N32 ABI too.Daniel Sanders2015-05-051-0/+3
| | | | | | | | | | | | | | | | | Summary: This required adding instruction aliases for dneg. N64 will be enabled shortly but requires additional bugfixes. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9341 llvm-svn: 236489
* [mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic.Toma Tabacu2015-04-081-1/+8
| | | | | | | | | | | | | | | | Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
* [mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.Toma Tabacu2015-03-171-0/+1
| | | | | | | | | | | | | | | | Summary: This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58". This should work for all MIPS ISAs. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8284 llvm-svn: 232473
* [mips] Add support for COP1's Branch-On-Cond-Likely instructionsVasileios Kalintiris2014-10-171-0/+4
| | | | | | | | | | | | Summary: Depends on D5782 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5802 llvm-svn: 220042
* [mips] Add support for COP0's Branch-On-Cond-Likely instructionsVasileios Kalintiris2014-10-171-0/+8
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
* [mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to ↵Toma Tabacu2014-09-161-0/+1
| | | | | | | | | | MipsInstrInfo.td. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5244 llvm-svn: 217868
* [mips] Marked the ADDi instruction aliases as not available in Mips32R6 and ↵Toma Tabacu2014-09-161-0/+4
| | | | | | | | | | Mips64R6. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5242 llvm-svn: 217867
* [mips] Marked the DADDiu instruction aliases as MIPS III.Toma Tabacu2014-09-151-0/+4
| | | | | | | | Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5239 llvm-svn: 217770
* [mips] Marked the Trap-on-Condition instructions as Mips IIDaniel Sanders2014-09-051-0/+12
| | | | | | | | | | | | Patch by Vasileios Kalintiris. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5173 llvm-svn: 217255
* [mips] SYNC $stype instruction was added in Mips32Matheus Almeida2014-06-181-0/+1
| | | | | | but SYNC with an implied operand ($stype = 0) is valid since Mips2. llvm-svn: 211185
* [mips] Update MipsAsmParser so that it's possible to handle immediates that ↵Matheus Almeida2014-06-181-0/+1
| | | | | | | | | | | | start with the binary operator NOT (~). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4158 llvm-svn: 211163
* [mips] Implement alias for 'and' and 'or' instructions for all ISAs.Matheus Almeida2014-06-181-0/+2
| | | | | | | | | | | | | | | Summary: Examples: and $2, 4 <=> andi $2, $2, 4 or $2, 4 <=> ori $2, $2, 4 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4155 llvm-svn: 211161
* [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.Daniel Sanders2014-06-161-4/+4
| | | | | | | | | | | | | | | | | | | | | Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
* [mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates ↵Daniel Sanders2014-06-161-4/+4
| | | | | | | | | | | | | | | | | | | | | rather than 16-bit in MIPS32r6/MIPS64r6 Summary: The error message for the invalid.s cases isn't very helpful. It happens because there is an instruction with a wider immediate that would have matched if the NotMips32r6 predicate were true. I have some WIP to improve the message but it affects most error messages for removed/re-encoded instructions on MIPS32r6/MIPS64r6 and should therefore be a separate commit. Depens on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4117 llvm-svn: 211012
* [mips] Add cache and pref instructionsDaniel Sanders2014-06-131-0/+1
| | | | | | | | | | | | | | | | | | | Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 llvm-svn: 210900
* [mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal ↵Daniel Sanders2014-06-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | is a normal instruction Summary: b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias for 'bgezal $zero, $offset') still remains with the same encoding it had prior to MIPS32r6/MIPS64r6. Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo. No changes were required to the CodeGen test that looks for BAL (test/CodeGen/Mips/longbranch.ll) since the new instruction has the same syntax. Depends on D4113 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4114 llvm-svn: 210898
* [mips][mips64r6] daddi is not available on MIPS64r6Daniel Sanders2014-06-131-0/+8
| | | | | | | | | | | | | | | | | | Summary: It's not emitted by the code generator so we only need assembler tests. Also added missing daddi aliases from dsub mnemonics, and removed a couple duplicate dsub tests. Depends on D4112 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4113 llvm-svn: 210897
* [mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-121-0/+4
| | | | | | | | | | | | | | | | | | | | Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 llvm-svn: 210787
* [mips] Added missing daddu test to the valid instruction tests.Daniel Sanders2014-05-091-0/+1
| | | | | | | | | | | | Summary: Depends on D3673 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3674 llvm-svn: 208398
* [mips] Added missing dsra -> dsrav and sra -> srav aliases.Daniel Sanders2014-05-091-0/+2
| | | | | | | | | | | | Summary: dsll, dsrl, sll, and srl already exist. Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3673 llvm-svn: 208397
* [mips] Correct tests that are meant to test valid assembly. They were ↵Daniel Sanders2014-05-081-169/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
* [mips] Implement tlbp, tlbr, tlbwi, and tlbwrDaniel Sanders2014-05-081-0/+4
| | | | | | | | | | Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3571 llvm-svn: 208301
* [mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-VDaniel Sanders2014-05-071-2/+1
| | | | | | | | | | | | | | | | | | | | Summary: These processors will only be available for the integrated assembler at first (CodeGen will emit a fatal error saying they are not implemented). The intention is to work through the existing instructions and correctly annotate the ISA they were added in so that we have a sufficiently good base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain instructions and I believe it is best to define ISA's using set-union's as far as possible rather than using set-subtraction. Reviewers: vmedic Subscribers: emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D3569 llvm-svn: 208221
* [mips] Removed two-operand alias for sllv, sr[al]v, rotrv, dsllv, dsr[al]v, ↵Daniel Sanders2014-05-011-6/+0
| | | | | | | | | | and drotrv GAS doesn't actually accept these particular cases. The mnemonic without the trailing 'v' still supports two-operand aliases. llvm-svn: 207740
* [mips] Add instruction alias (negu).Matheus Almeida2014-04-301-0/+2
| | | | | | | | | | | | Summary: negu $reg is equivalent to negu $reg, $reg. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3510 llvm-svn: 207673
* [mips] Add instruction alias (sltu).Matheus Almeida2014-04-301-0/+1
| | | | | | | | | | | | | | Summary: The pattern sltu $r1, $r2, $imm is found in handwritten assembly which is just a shorthand version of sltui $r1, $r2, $imm. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3508 llvm-svn: 207671
* [mips] Add instruction alias (dsll and dsrl).Matheus Almeida2014-04-301-0/+2
| | | | | | | | | | | | | | Summary: The pattern dsll/dsrl $rd, $rt, $rs is found in handwritten assembly which is just a shorthand version of dsllv/dsrlv $rd, $rt, $rs. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3486 llvm-svn: 207664
* [mips] Add instruction alias (sll and srl).Matheus Almeida2014-04-301-0/+2
| | | | | | | | | | | | | | Summary: The pattern sll/srl $rd, $rt, $rs is found in handwritten assembly which is just a shorthand version of sllv/srlv $rd, $rt, $rs. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3483 llvm-svn: 207657
* [mips] Update tests with encoding information for slt, slti, sltiu and sltu.Matheus Almeida2014-04-301-4/+4
| | | | | | | | | | | | | | Summary: Also renamed non-portable register names (e.g. $t2) so that we don't end up with a different encoding for what appears to be an equivalent instruction. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3505 llvm-svn: 207655
* [mips] Use TwoOperandAliasConstraint for shift instructions.Matheus Almeida2014-04-161-8/+32
| | | | | | | | | | This enables TableGen to generate an additional two operand matcher for our shift_rotate_imm and shift_rotate_reg class of instructions. The tests were also updated so that they include now encoding information for all affected instructions. llvm-svn: 206398
* [mips] Switch the MIPS-III and MIPS-IV assembler tests to use -mcpu=mips4.Daniel Sanders2014-04-101-3/+3
| | | | | | | | | | | | | | | | | | Summary: It is now the smallest superset for these ISA's. FeatureMips4 now contains FeatureFPIdx since [ls][dw]xc1 were added in MIPS-IV. Made the FPIdx feature bit lowercase so that it can be used in the -mattr option. Depends on D3274 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3275 llvm-svn: 205964
* [mips] Implement ehb, ssnop, and pause in assemblerDaniel Sanders2014-04-031-0/+2
| | | | | | | | | | | | Summary: Add negative tests for pause Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3246 llvm-svn: 205537
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