| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [AArch64][SVE] Re-submit patch series for ZIP1/ZIP2 | Sander de Smalen | 2017-12-20 | 1 | -7/+7 |
| * | Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turbo | Reid Kleckner | 2017-12-18 | 1 | -7/+7 |
| * | [TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled ins... | Sander de Smalen | 2017-12-18 | 1 | -7/+7 |
| * | [mips] Correct c.cond.fmt instruction definition. | Simon Dardis | 2017-01-16 | 1 | -2/+2 |
| * | [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2... | Zlatko Buljan | 2016-07-11 | 1 | -2/+0 |
| * | [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instruct... | Hrvoje Varga | 2016-06-27 | 1 | -4/+0 |
| * | [mips] Range check simm16 | Daniel Sanders | 2016-03-31 | 1 | -4/+4 |
| * | [mips] Range check simm11 and mem_simm11. | Daniel Sanders | 2016-03-31 | 1 | -2/+4 |
| * | [mips] Range check simm9 and fix a bug this revealed. | Daniel Sanders | 2016-03-31 | 1 | -4/+4 |
| * | [mips] Add support for COP1's Branch-On-Cond-Likely instructions | Vasileios Kalintiris | 2014-10-17 | 1 | -0/+2 |
| * | [mips] Marked up instructions added in MIPS-IV and tested that IAS for -mcpu=... | Daniel Sanders | 2014-05-09 | 1 | -0/+23 |
