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* [mips] Correct the definitions of some control instructionsSimon Dardis2018-04-261-4/+15
| | | | | | | | | | | | | | Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
* [mips] Fix the definitions of the EVA instructionsSimon Dardis2018-03-131-24/+1
| | | | | | | | | | Correct their availability to their respective ISAs. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D44209 llvm-svn: 327403
* [mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI ↵Hrvoje Varga2015-10-281-8/+8
| | | | | | | | and WAIT instructions Differential Revision: http://reviews.llvm.org/D12628 llvm-svn: 251510
* [mips][microMIPS] Implement LLE and SCE instructionsHrvoje Varga2015-10-151-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D11630 llvm-svn: 250379
* [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructionsHrvoje Varga2015-10-151-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D11631 llvm-svn: 250377
* [mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and ↵Zoran Jovanovic2015-09-161-0/+3
| | | | | | | | SWE instructions Differential Revision: http://reviews.llvm.org/D9189 llvm-svn: 247780
* [mips][microMIPS] Implement CACHEE and PREFE instructionsZoran Jovanovic2015-09-091-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D11628 llvm-svn: 247125
* [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructionsJozef Kolek2014-12-231-0/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D5204 llvm-svn: 224785
* [mips][microMIPS] Implement SDBBP and RDHWR instructions.Jozef Kolek2014-11-191-0/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D5240 llvm-svn: 222347
* [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructionsZoran Jovanovic2014-09-121-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D5211 llvm-svn: 217675
* [mips] Marked up instructions added in MIPS32r2 and tested that IAS for ↵Daniel Sanders2014-05-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
* TableGen: use PrintMethods to print more aliasesTim Northover2014-05-121-2/+2
| | | | llvm-svn: 208607
* Provide an operand for microMIPS wait instruction.Zoran Jovanovic2014-03-201-0/+3
| | | | llvm-svn: 204329
* Fixed encoding of SYSCALL microMIPS instruction.Zoran Jovanovic2014-02-281-5/+5
| | | | llvm-svn: 202523
* Revert revision 202518 because of wrong commit message.Zoran Jovanovic2014-02-281-5/+5
| | | | llvm-svn: 202521
* Fix operand of SC instruction.Zoran Jovanovic2014-02-281-5/+5
| | | | llvm-svn: 202518
* Support for microMIPS control instructions.Zoran Jovanovic2013-12-191-0/+57
llvm-svn: 197696
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