bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	[mips] Move test case for Octeon instructions to cnmips sub-folder. NFC	Simon Atanasyan	2019-11-04	1	-0/+118
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*	[mips] Correct the predicates of the load/store (double)word for coprocessor 3.	Simon Dardis	2018-04-12	1	-0/+8
\| \| \| \|	llvm-svn: 329913
*	[mips] Range check simm10	Daniel Sanders	2016-03-24	1	-0/+4
\| \| \| \| \| \| \| \| \| \| \| \|	Summary: Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18148 llvm-svn: 264279
*	[mips][microMIPS] Implement DINSU, DINSM, DINS instructions	Hrvoje Varga	2016-02-25	1	-0/+4
\| \| \| \| \| \|	Differential Revision: http://reviews.llvm.org/D16181 llvm-svn: 261860
*	[mips][ias] Range check uimm5 operands and fix several bugs this revealed.	Daniel Sanders	2015-11-26	1	-0/+15
	Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164