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* [X86][Disassembler] Add bizarro versions of the MOVSXD instruction that sign ↵Craig Topper2018-10-021-0/+9
| | | | | | | | | | extend from a GR32 to GR32 or GR16. The 0x63 opcodes in 64-bit mode have a fixed source size of 32-bits, but the destination size is controlled by REX.W and the 0x66 opsize prefix. This instruction is normally used with a REX.W prefix which provides desired behavior. The other encodings are interpretted as valid by the processor, but aren't useful. This patch makes us recognize them for the disassembler to match objdump. llvm-svn: 343614
* [AArch64][v8.5A] Add Memory Tagging instructionsOliver Stannard2018-10-022-3/+455
| | | | | | | | | | | This adds new instructions to manipluate tagged pointers, and to load and store the tags associated with memory. Patch by Pablo Barrio, David Spickett and Oliver Stannard! Differential revision: https://reviews.llvm.org/D52490 llvm-svn: 343572
* [AArch64][v8.5A] Add Memory Tagging system registersOliver Stannard2018-10-021-2/+42
| | | | | | | | | | | This adds new system registers introduced by the Memory Tagging extension. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52488 llvm-svn: 343571
* [AArch64][v8.5A] Add MTE system instructionsOliver Stannard2018-10-021-0/+60
| | | | | | | | | | | The Memory Tagging Extension adds system instructions for data cache maintenance, implemented as new operands to the DC instruction. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52487 llvm-svn: 343570
* [ARM][v8.5A] Add speculation barriers SSBB and PSSBBOliver Stannard2018-09-282-4/+4
| | | | | | | | | | | This adds two new barrier instructions which can be used to restrict speculative execution of load instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52484 llvm-svn: 343300
* [AArch64][v8.5A] Add speculation barriers SSBB and PSSBBOliver Stannard2018-09-272-3/+6
| | | | | | | | | | | This adds two new barrier instructions which can be used to restrict speculative execution of load instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52483 llvm-svn: 343229
* [AArch64][v8.5A] Add Branch Target Identification instructionsOliver Stannard2018-09-271-0/+18
| | | | | | | | | | | | This adds new instructions used by the Branch Target Identification feature. When this is enabled, these are the only instructions which can be targeted by indirect branch instructions. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52485 llvm-svn: 343225
* [AArch64][v8.5A] Add speculation restriction system registersOliver Stannard2018-09-271-0/+52
| | | | | | | | | | | This adds some new system registers which can be used to restrict certain types of speculative execution. Patch by Pablo Barrio and David Spickett! Differential revision: https://reviews.llvm.org/D52482 llvm-svn: 343218
* [AArch64][v8.5A] Add Armv8.5-A random number instructionsOliver Stannard2018-09-271-0/+12
| | | | | | | | | | | | | This adds two new system registers, used to generate random numbers. This is an optional extension to v8.5-A, and will be controlled by the "+rng" modifier of the -march= and -mcpu= options. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52481 llvm-svn: 343217
* [AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instructionOliver Stannard2018-09-271-0/+7
| | | | | | | | | | | This adds a new variant of the DC system instruction for persistent memory. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52480 llvm-svn: 343216
* [AArch64][v8.5A] Add prediction invalidation instructions to AArch64Oliver Stannard2018-09-271-0/+15
| | | | | | | | | | | | This adds new system instructions which act as barriers to speculative execution based on earlier execution within a particular execution context. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52479 llvm-svn: 343214
* [ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction setsOliver Stannard2018-09-272-0/+18
| | | | | | | | | | | This is a new barrier which limits speculative execution of the instructions following it. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52477 llvm-svn: 343213
* [AArch64][v8.5A] Add speculation barrier to AArch64 instruction setOliver Stannard2018-09-271-0/+9
| | | | | | | | | | | This is a new barrier which limits speculative execution of the instructions following it. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52476 llvm-svn: 343211
* [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructionsOliver Stannard2018-09-271-5/+94
| | | | | | | | | | | | These are some new variants of the "Floating-point Round to Integral" family of instructions, which round to the nearest floating-point value which fits in a 32- or 64-bit integer. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52475 llvm-svn: 343209
* [AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlagOliver Stannard2018-09-271-0/+12
| | | | | | | | | | | These new instructions manipluate the NZCV bits, to convert between the regular Arm floating-point comare format and an alternative format. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52473 llvm-svn: 343187
* [RISCV] Fix decoding of invalid instruction with C extension enabled.Ana Pazos2018-09-131-0/+13
| | | | | | | | | | | | | | | | | | | | | | Summary: The illegal instruction 0x00 0x00 is being wrongly decoded as c.addi4spn with 0 immediate. The invalid instruction 0x01 0x61 is being wrongly decoded as c.addi16sp with 0 immediate. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D51815 llvm-svn: 342159
* [WebAssembly] v8x16.shuffleThomas Lively2018-09-071-0/+3
| | | | | | | | | | | | | | | | | | Summary: Since the shuffle mask is not exposed as an operand in the native ISel DAG, create a new WebAssembly ISD node exposing the mask. The mask is lowered as sixteen immediate byte indices no matter what type the original vector shuffle was operating on. This CL depends on D51656 Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51659 llvm-svn: 341718
* [RISCV] Fix crash in decoding instruction with unknown floating point ↵Ana Pazos2018-09-071-0/+9
| | | | | | | | | | | | | | | | | | | | rounding mode Summary: Instead of crashing in printFRMArg, decode and warn about invalid instruction. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D51705 llvm-svn: 341691
* [RISCV] Fix AddressSanitizer heap-buffer-overflow in disassemblingAna Pazos2018-09-072-0/+11
| | | | | | | | | | | | | | | | | | Summary: RISCVDisassembler should check number of bytes available before reading them. Crash noticed when enabling -DLLVM_USE_SANITIZER=Address. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D51708 llvm-svn: 341686
* [ARC] Prevent InstPrinter from crashing on unknown condition codes.Tatyana Krasnukha2018-09-061-0/+2
| | | | | | | | | | | | | Summary: Instruction printer shouldn't crash with assertions due to incorrect input data. llvm_unreachable is not intended for runtime error handling. Reviewers: petecoup Reviewed By: petecoup Differential Revision: https://reviews.llvm.org/D51728 llvm-svn: 341581
* [WebAssembly] Made disassembler only use stack instructions.Wouter van Oortmerssen2018-08-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Now uses the StackBased bit from the tablegen defs to identify stack instructions (and ignore register based or non-wasm instructions). Also changed how we store operands, since we now have up to 16 of them per instruction. To not cause static data bloat, these are compressed into a tiny table. + a few other cleanups. Tested: - MCTest - llvm-lit -v `find test -name WebAssembly` Reviewers: dschuff, jgravelle-google, sunfish, tlively Subscribers: sbc100, aheejin, llvm-commits Differential Revision: https://reviews.llvm.org/D51320 llvm-svn: 341081
* [mips] Add missing instructionsAleksandar Beserminji2018-08-296-0/+42
| | | | | | | | Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64. Differential Revision: https://reviews.llvm.org/D50437 llvm-svn: 340920
* [WebAssembly] Added default stack-only instruction mode for MC.Wouter van Oortmerssen2018-08-271-2/+1
| | | | | | | | | | | | | | | | | | | | | Summary: Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D51241 llvm-svn: 340750
* [WebAssembly] v128.constThomas Lively2018-08-211-0/+4
| | | | | | | | | | | | | | | | Summary: This CL implements v128.const for each vector type. New operand types are added to ensure the vector contents can be serialized without LEB encoding. Tests are added for instruction selection, encoding, assembly and disassembly. Reviewers: aheejin, dschuff, aardappel Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D50873 llvm-svn: 340336
* [ARM/AArch64] Support FP16 +fp16fml instructionsBernard Ogden2018-08-174-0/+328
| | | | | | | | | | | | | | | | | | Add +fp16fml feature for new FP16 instructions, which are a mandatory part of FP16 from v8.4-A and an optional part of FP16 from v8.2-A. It doesn't seem to be possible to model this in LLVM, but the relationship between the options is handled by the related clang patch. In keeping with what I think is the usual practice, the fp16fml extension is accepted regardless of base architecture version. Builds on/replaces Sjoerd Meijer's patch to add these instructions at https://reviews.llvm.org/D49839. Differential Revision: https://reviews.llvm.org/D50228 llvm-svn: 340013
* Revert "[WebAssembly] Added default stack-only instruction mode for MC."Wouter van Oortmerssen2018-08-131-1/+2
| | | | | | This reverts commit 917a99b71ce21c975be7bfbf66f4040f965d9f3c. llvm-svn: 339630
* [X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode ↵Craig Topper2018-08-131-36/+48
| | | | | | | | | | | | | | | | selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions. The behavior in 64-bit mode is different between Intel and AMD CPUs. Intel ignores the 0x66 prefix. AMD does not. objump doesn't ignore the 0x66 prefix. Since LLVM aims to match objdump behavior, we should do the same. While I was trying to fix this I had change brtarget16/32 to use ENCODING_IW/ID instead of ENCODING_Iv to get the 0x66+REX.W case to act sort of sanely. It's still wrong, but that's a problem for another day. The change in encoding exposed the fact that 16-bit mode disassembly of relative jumps was creating JMP_4 with a 2 byte immediate. It should have been JMP_2. From just printing you can't tell the difference, but if you dumped the encoding it wouldn't have matched what we started with. While fixing that, it exposed that jo/jno opcodes were missing from the switch that this patch deleted and there were no test cases for them. Fixes PR38537. llvm-svn: 339622
* [WebAssembly] Added default stack-only instruction mode for MC.Wouter van Oortmerssen2018-08-101-2/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: Moved Explicit Locals pass to last. Made that pass obligatory. Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: jfb, llvm-commits, aheejin, eraman, jgravelle-google, sbc100 Differential Revision: https://reviews.llvm.org/D50568 llvm-svn: 339474
* Revert "[WebAssembly] Added default stack-only instruction mode for MC."Wouter van Oortmerssen2018-07-271-1/+2
| | | | | | | This reverts commit d3c9af4179eae7793d1487d652e2d4e23844555f. (SVN revision 338164) llvm-svn: 338176
* [WebAssembly] Added default stack-only instruction mode for MC.Wouter van Oortmerssen2018-07-271-2/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: Moved Explicit Locals pass to last. Made that pass obligatory. Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits Differential Revision: https://reviews.llvm.org/D49160 llvm-svn: 338164
* [AArch64] Armv8.2-A: add the crypto extensionsSjoerd Meijer2018-07-261-0/+93
| | | | | | | | | This adds MC support for the crypto instructions that were made optional extensions in Armv8.2-A (AArch64 only). Differential Revision: https://reviews.llvm.org/D49370 llvm-svn: 338010
* Complete the SPE instruction set patternsJustin Hibbits2018-07-181-2/+513
| | | | | | | | | This is the lead-up to having SPE codegen. Add the rest of the instructions, along with MC tests. Differential Revision: https://reviews.llvm.org/D44829 llvm-svn: 337346
* Follow up of r336913: forgot to add the new test files.Sjoerd Meijer2018-07-121-0/+277
| | | | llvm-svn: 336914
* [AArch64] Armv8.4-A: TLB supportSjoerd Meijer2018-07-061-0/+151
| | | | | | | | This adds: - outer shareable TLB Maintenance instructions, and - TLB range maintenance instructions. llvm-svn: 336434
* Recommit: [AArch64] Armv8.4-A: Flag manipulation instructionsSjoerd Meijer2018-07-061-0/+11
| | | | | | Now with the asm operand definition included. llvm-svn: 336432
* Revert [AArch64] Armv8.4-A: Flag manipulation instructionsSjoerd Meijer2018-07-061-11/+0
| | | | | | It's causing build errors. llvm-svn: 336422
* [AArch64] Armv8.4-A: Flag manipulation instructionsSjoerd Meijer2018-07-061-0/+11
| | | | | | | | These instructions are added to AArch64 only. Differential Revision: https://reviews.llvm.org/D48926 llvm-svn: 336421
* [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instructionSjoerd Meijer2018-07-063-0/+23
| | | | | | | | This adds the Armv8.4-A Trace synchronization barrier (TSB) instruction. Differential Revision: https://reviews.llvm.org/D48918 llvm-svn: 336418
* [X86][Disassembler] Fix LOCK prefix disassembler supportMaksim Panchenko2018-07-051-0/+4
| | | | | | | | | | | | | | | | | | | Summary: If LOCK prefix is not the first prefix in an instruction, LLVM disassembler silently drops the prefix. The fix is to select a proper instruction with a builtin LOCK prefix if one exists. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D49001 llvm-svn: 336400
* NFC - Various typo fixes in testsGabor Buella2018-07-041-1/+1
| | | | llvm-svn: 336268
* [AArch64] Armv8.4-A: system registersSjoerd Meijer2018-07-036-0/+451
| | | | | | | | | | | | | | This adds the following system registers: - RAS registers, - MPAM registers, - Activitiy monitor registers, - Trace Extension registers, - Timing insensitivity of data processing instructions, - Enhanced Support for Nested Virtualization. Differential Revision: https://reviews.llvm.org/D48871 llvm-svn: 336193
* [AArch64] Armv8.4-A: Virtualization system registersSjoerd Meijer2018-06-291-0/+39
| | | | | | | | This adds the Secure EL2 extension. Differential Revision: https://reviews.llvm.org/D48711 llvm-svn: 335962
* [X86] Teach the disassembler to use %eiz/%riz instead of NoRegister when the ↵Craig Topper2018-06-272-8/+38
| | | | | | | | | | SIB byte is present, but doesn't encode an index register and there was another shorter encoding that would achieve the same result. The %eiz/%riz are dummy registers that force the encoder to emit a SIB byte when it normally wouldn't. By emitting them in the disassembly output we ensure that assembling the disassembler output would also produce a SIB byte. This should match the behavior of objdump from binutils. llvm-svn: 335768
* ARM: correctly decode VFP instructions following unpredictable t2ITTim Northover2018-06-261-6/+6
| | | | | | | | | When the condition code for an IT instruction is "AL" we get strange "15" predicates on subsequent instructions. These are dealt with for most instructions by treating them as "ARMCC::AL", but VFP takes a different path which didn't have this code. llvm-svn: 335594
* [PowerPC] Fix incorrectly encoded wait instructionLei Huang2018-06-251-4/+4
| | | | | | | | Encoding for the wait instruction was wrong. Fix according to ISA 3.0. Differential Revision: https://reviews.llvm.org/D48550 llvm-svn: 335514
* [X86] Teach disassembler to use %eip instead of %rip when 0x67 prefix is ↵Craig Topper2018-06-231-0/+4
| | | | | | used on a rip-relative address. llvm-svn: 335413
* [WebAssembly] Modified tablegen defs to have 2 parallel instuction sets.Wouter van Oortmerssen2018-06-181-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: One for register based, much like the existing definitions, and one for stack based (suffix _S). This allows us to use registers in most of LLVM (which works better), and stack based in MC (which results in a simpler and more readable assembler / disassembler). Tried to keep this change as small as possible while passing tests, follow-up commit will: - Add reg->stack conversion in MI. - Fix asm/disasm in MC to be stack based. - Fix emitter to be stack based. tests passing: llvm-lit -v `find test -name WebAssembly` test/CodeGen/WebAssembly test/MC/WebAssembly test/MC/Disassembler/WebAssembly test/DebugInfo/WebAssembly test/CodeGen/MIR/WebAssembly test/tools/llvm-objdump/WebAssembly Reviewers: dschuff, sbc100, jgravelle-google, sunfish Subscribers: aheejin, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D48183 llvm-svn: 334985
* [X86] Properly disassemble gather/scatter instructions where xmm4/ymm4/zmm4 ↵Craig Topper2018-06-061-0/+3
| | | | | | | | | | are used as the index. These encodings correspond to the cases in the normal encoding scheme where there is no index and our modrm reading code initially decodes it as such. The VSIB handling code tried to compensate for this, but failed to add the base needed to make later code do the right thing. Fixes PR37712. llvm-svn: 334121
* [X86][Disassembler] Make it an error to set EVEX.R' to 0 when modrm.reg ↵Craig Topper2018-06-011-0/+4
| | | | | | | | encodes a GPR. This is different than the behavior of EVEX.X extending modrm.rm to 5 bits. llvm-svn: 333728
* [X86][Disassembler] Ignore EVEX.X extension of modrm.rm to 5-bits when ↵Craig Topper2018-06-011-0/+5
| | | | | | modrm.rm encodes a k-register. llvm-svn: 333727
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