| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit m... | Craig Topper | 2014-10-07 | 1 | -0/+3 |
| * | [mips] Fix disassembly of [ls][wd]c[23], cache, and pref ... | Daniel Sanders | 2014-10-01 | 3 | -0/+32 |
| * | Thumb2 M-class MSR instruction support changes | Renato Golin | 2014-09-01 | 2 | -13/+14 |
| * | [PowerPC] Add support for dcbtst and icbt (prefetch) | Hal Finkel | 2014-08-23 | 1 | -0/+3 |
| * | ARM: implement MRS/MSR (banked reg) system instructions. | Tim Northover | 2014-08-15 | 2 | -0/+303 |
| * | Update disassembler test to check the full dccci/iccci form. | Joerg Sonnenberger | 2014-08-09 | 1 | -4/+4 |
| * | Add RFID instruction. | Joerg Sonnenberger | 2014-08-07 | 1 | -0/+3 |
| * | Add dci/ici instructions for PPC 476 and friends. | Joerg Sonnenberger | 2014-08-05 | 1 | -0/+5 |
| * | Add lswi / stswi for assembler use with a warning to not add patterns | Joerg Sonnenberger | 2014-08-05 | 1 | -0/+5 |
| * | Add PPC 603's tlbld and tlbli instructions. | Joerg Sonnenberger | 2014-08-04 | 1 | -0/+6 |
| * | tlbre / tlbwe / tlbsx / tlbsx. variants for the PPC 4xx CPUs. | Joerg Sonnenberger | 2014-08-04 | 1 | -0/+15 |
| * | Add features for PPC 4xx and e500/e500mc instructions. | Joerg Sonnenberger | 2014-08-04 | 3 | -10/+13 |
| * | tlbia support | Joerg Sonnenberger | 2014-08-02 | 1 | -0/+3 |
| * | mfdcr / mtdcr support | Joerg Sonnenberger | 2014-08-02 | 1 | -0/+5 |
| * | Don't use additional arguments for dss and friends to satisfy DSS_Form, | Joerg Sonnenberger | 2014-08-02 | 1 | -0/+13 |
| * | Allow only disassembling of M-class MSR masks that the assembler knows how to... | James Molloy | 2014-08-01 | 2 | -4/+125 |
| * | Refactor TLBIVAX and add tlbsx. | Joerg Sonnenberger | 2014-07-30 | 1 | -0/+2 |
| * | Add rfdi and rfmci from the e500/e500mc ISA. | Joerg Sonnenberger | 2014-07-30 | 1 | -0/+4 |
| * | Add BookE's tlbre, tlbwe and tlbivax instructions. | Joerg Sonnenberger | 2014-07-30 | 1 | -0/+7 |
| * | Add BookE's wrtee and wrteei instructions. | Joerg Sonnenberger | 2014-07-30 | 1 | -0/+7 |
| * | Add rfci instruction. | Joerg Sonnenberger | 2014-07-29 | 1 | -0/+2 |
| * | Recognize BookE's mbar instruction. | Joerg Sonnenberger | 2014-07-29 | 1 | -0/+3 |
| * | Support move to/from segment register. | Joerg Sonnenberger | 2014-07-29 | 1 | -0/+4 |
| * | Add rfi instruction. Based on feedback by Ulrich Weigand. | Joerg Sonnenberger | 2014-07-29 | 1 | -0/+2 |
| * | [X86] AVX512: Add disassembler support for compressed displacement | Adam Nemet | 2014-07-17 | 1 | -0/+39 |
| * | [SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRA | Richard Sandiford | 2014-07-10 | 1 | -0/+54 |
| * | [mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions | Daniel Sanders | 2014-07-09 | 2 | -40/+40 |
| * | [mips][mips64r6] Correct the encoding of dmuh, dmuhu, dmul, and dmulu. | Daniel Sanders | 2014-07-04 | 1 | -4/+4 |
| * | [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fields | Adam Nemet | 2014-06-24 | 1 | -0/+6 |
| * | [mips][mips64r6] Add BLTC and BLTUC instructions | Zoran Jovanovic | 2014-06-18 | 2 | -0/+4 |
| * | [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6 | Daniel Sanders | 2014-06-16 | 2 | -0/+6 |
| * | [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. | Daniel Sanders | 2014-06-16 | 2 | -0/+6 |
| * | [mips][mips64r6] Add bgec and bgeuc instructions | Zoran Jovanovic | 2014-06-12 | 2 | -0/+4 |
| * | ARM: honor hex immediate formatting for ldr/str i12 offsets. | Jim Grosbach | 2014-06-11 | 1 | -0/+6 |
| * | llvm-mc: Add option for prefering hex format disassembly. | Jim Grosbach | 2014-06-11 | 3 | -5/+5 |
| * | [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register ... | Matheus Almeida | 2014-06-11 | 2 | -0/+6 |
| * | Condition codes AL and NV are invalid in the aliases that use | Artyom Skrobov | 2014-06-10 | 1 | -2/+20 |
| * | Reduce verbiage of lit.local.cfg files | Alp Toker | 2014-06-09 | 8 | -16/+8 |
| * | [mips][mips64r6] Add LDPC instruction | Zoran Jovanovic | 2014-06-09 | 1 | -0/+1 |
| * | Restore getInvertedCondCode() from the phased-out backend, fixing disassembly... | Artyom Skrobov | 2014-05-29 | 1 | -2/+4 |
| * | AArch64/ARM64: move ARM64 into AArch64's place | Tim Northover | 2014-05-24 | 16 | -6/+1 |
| * | AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64. | Tim Northover | 2014-05-24 | 1 | -1/+1 |
| * | [mips][mips64r6] Add b[on]vc | Daniel Sanders | 2014-05-22 | 2 | -0/+245 |
| * | TableGen: fix operand counting for aliases | Tim Northover | 2014-05-16 | 2 | -7/+7 |
| * | ARM64: print correct aliases for NEON mov & mvn instructions | Tim Northover | 2014-05-15 | 1 | -5/+5 |
| * | TableGen/ARM64: print aliases even if they have syntax variants. | Tim Northover | 2014-05-15 | 2 | -6/+4 |
| * | ARM: implement support for the UDF mnemonic | Saleem Abdulrasool | 2014-05-14 | 1 | -39/+0 |
| * | TableGen: use PrintMethods to print more aliases | Tim Northover | 2014-05-12 | 1 | -28/+28 |
| * | [mips] Move disassembler test (test_2r_msa64) into correct folder. | Matheus Almeida | 2014-05-12 | 1 | -0/+3 |
| * | [mips] Move disassembler test (Mips MSA test_vec) into correct folder. | Matheus Almeida | 2014-05-12 | 1 | -0/+9 |
