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* AMDGPU/SI: Assembler: Unify parsing/printing of operands.Nikolay Haustov2016-04-291-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The goal is for each operand type to have its own parse function and at the same time share common code for tracking state as different instruction types share operand types (e.g. glc/glc_flat, etc). Introduce parseAMDGPUOperand which can parse any optional operand. DPP and Clamp/OMod have custom handling for now. Sam also suggested to have class hierarchy for operand types instead of table. This can be done in separate change. Remove parseVOP3OptionalOps, parseDS*OptionalOps, parseFlatOptionalOps, parseMubufOptionalOps, parseDPPOptionalOps. Reduce number of definitions of AsmOperand's and MatchClasses' by using common base class. Rename AsmMatcher/InstPrinter methods accordingly. Print immediate type when printing parsed immediate operand. Use 'off' if offset/index register is unused instead of skipping it to make it more readable (also agreed with SP3). Update tests. Reviewers: tstellarAMD, SamWot, artem.tamazov Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19584 llvm-svn: 268015
* This reverts commit r265505.Kit Barton2016-04-281-44/+0
| | | | | | | Revert "[Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance". This patch has caused a functional regression in SPEC2k6 namd, and a performance regression in mesa-pipe. llvm-svn: 267927
* [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware ↵Artem Tamazov2016-04-271-3/+9
| | | | | | | | | | | | registers. Possibility to specify code of hardware register kept. Disassemble to symbolic name, if name is known. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19335 llvm-svn: 267724
* [mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU ↵Zlatko Buljan2016-04-271-0/+6
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16676 llvm-svn: 267694
* [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, ↵Zlatko Buljan2016-04-272-0/+11
| | | | | | | | SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
* [mips][microMIPS] Revert commit r267137Hrvoje Varga2016-04-251-4/+0
| | | | | | Commit r267137 was the reason for failing tests in LLVM test suite. llvm-svn: 267419
* [mips][microMIPS] Revert commit r266977Zlatko Buljan2016-04-254-24/+0
| | | | | | Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ... llvm-svn: 267418
* [AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax.Artem Tamazov2016-04-251-5/+5
| | | | | | | | | | | | | Added hwreg(reg[,offset,width]) syntax. Default offset = 0, default width = 32. Possibility to specify 16-bit immediate kept. Added out-of-range checks. Disassembling is always to hwreg(...) format. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19329 llvm-svn: 267410
* [mips][microMIPS] Revert commit r266861.Zoran Jovanovic2016-04-221-6/+0
| | | | | | Commit r266861 was the reason for failing tests in LLVM test suite. llvm-svn: 267166
* [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructionsHrvoje Varga2016-04-221-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D19354 llvm-svn: 267137
* [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructionsZlatko Buljan2016-04-222-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D18687 llvm-svn: 267114
* [mips][microMIPS] Implement ldpc instructionZoran Jovanovic2016-04-211-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D15009 llvm-svn: 266990
* [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructionsZlatko Buljan2016-04-212-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D18855 llvm-svn: 266980
* [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL ↵Zlatko Buljan2016-04-214-0/+24
| | | | | | | | instructions and add tests for LWM32 and SWM32 Differential Revision: http://reviews.llvm.org/D19150 llvm-svn: 266977
* [mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructionsZoran Jovanovic2016-04-201-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
* [mips][microMIPS]Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-04-201-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D18640 llvm-svn: 266861
* [LLVM] Remove unwanted --check-prefix=CHECK from unit tests. NFC.Mandeep Singh Grang2016-04-191-1/+1
| | | | | | | | | | | | Summary: Removed unwanted --check-prefix=CHECK from numerous unit tests. Reviewers: t.p.northover, dblaikie, uweigand, MatzeB, tstellarAMD, mcrosier Subscribers: mcrosier, dsanders Differential Revision: http://reviews.llvm.org/D19279 llvm-svn: 266834
* [AMDGPU][llvm-mc] s_setreg* - Fix order of operandsArtem Tamazov2016-04-181-2/+2
| | | | | | | | Order should match the sp3 syntax, where destination (simm16 denoting the hwreg) is coming first. Differential Revision: http://reviews.llvm.org/D19161 llvm-svn: 266617
* Summary:Simon Dardis2016-04-144-0/+8
| | | | | | | | | | Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. This patch was previous committed as r266055 as seemed to have caused some spurious test failures. They did not reappear after further local testing. llvm-svn: 266301
* [PowerPC] Basic support for P9 byte comparison and count trailing zero insnsNemanja Ivanovic2016-04-131-0/+18
| | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D17850 This patch implements the following instructions: cmprb, cmpeqb, cnttzw, cnttzw., cnttzd, cnttzd. llvm-svn: 266228
* [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, ↵Zlatko Buljan2016-04-131-4/+4
| | | | | | | | | | | | DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068. There was the problem with test-suite failure. The problem is hopefully solved with dependant patch so this patch is commited again. llvm-svn: 266179
* Revert "[mips] MIPSR6 Compact branch aliases"Simon Dardis2016-04-124-8/+0
| | | | | | | | This reverts commit r266055. ps4-buildslave2 is highlighting a failure. llvm-svn: 266061
* [mips] MIPSR6 Compact branch aliasesSimon Dardis2016-04-124-0/+8
| | | | | | | | | | | | Summary: Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D18856 llvm-svn: 266055
* [SystemZ] Add SVC instructionUlrich Weigand2016-04-111-0/+12
| | | | | | | | | This is going to be useful for inline assembly only. Author: koriakin Differential Revision: http://reviews.llvm.org/D18952 llvm-svn: 265943
* [mips][microMIPS] Add CodeGen support for ADD, ADDIU*, ADDU* and DADD* ↵Zlatko Buljan2016-04-081-0/+22
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16454 llvm-svn: 265772
* [AMDGPU] Add some VI disassembler tests missing from previous autogeneration ↵Valery Pykhtin2016-04-081-0/+66
| | | | | | due to different filecheck prefix. NFC. llvm-svn: 265769
* [AMDGPU] fix readlane/readfirstlane src vgpr operand type.Valery Pykhtin2016-04-072-2/+5
| | | | | | | | | For VGPR_32 operand disassembler expects a VGPR register encoded as 0..255 (enum8 src operand). readfirstlane/readline actually has enum9 operand and this change fixes VGPR_32 to VS_32 (enum9 encoding). Differential Revision: http://reviews.llvm.org/D18696 llvm-svn: 265670
* [Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random ↵Chuang-Yu Cheng2016-04-061-0/+44
| | | | | | | | | | | | | | | | | | | | | number, set bool, and dfp test significance This patch implement the following instructions: - addpcis subpcis - maddhd maddhdu maddld - modsw moduw modsd modud - darn - extswsli extswsli. - setb - dtstsfi dtstsfiq Total 15 instructions Reviewers: nemanjai hfinkel tjablin amehsan kbarton http://reviews.llvm.org/D17885 llvm-svn: 265505
* [Power9] Implement copy-paste, msgsync, slb, and stop instructionsChuang-Yu Cheng2016-04-061-0/+21
| | | | | | | | | | | | | This patch implements the following BookII and Book III instructions: - copy copy_first cp_abort paste paste. paste_last - msgsync - slbieg slbsync - stop Total 10 instructions Reviewers: nemanjai hfinkel tjablin amehsan kbarton llvm-svn: 265504
* [SystemZ] Add compare-and-branch instructions to MCUlrich Weigand2016-04-041-0/+552
| | | | | | | | | | | | This adds MC support for fused compare + indirect branch instructions, ie. CRB, CGRB, CLRB, CLGRB, CIB, CGIB, CLIB, CLGIB. They aren't actually generated yet -- this is preparation for their use for conditional returns in the next iteration of D17339. Author: koriakin Differential Revision: http://reviews.llvm.org/D18742 llvm-svn: 265296
* [mips][microMIPS] Revert commits r264245 and r264248.Zoran Jovanovic2016-04-021-4/+4
| | | | | | | Commit r264245 was the reason for failing tests in LLVM test suite. Commit r264248 depends on the first one. llvm-svn: 265249
* [AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields.Valery Pykhtin2016-04-011-8/+8
| | | | | | | | $vsrc1 -> $src1, $k -> $imm Differential Revision: http://reviews.llvm.org/D18659 llvm-svn: 265141
* [PPC] basic support for Power 9 direct move instructionsEhsan Amiri2016-03-311-0/+9
| | | | | | | | http://reviews.llvm.org/D18097 Initial support does not include any patterns to generate this instructions llvm-svn: 265031
* [AMDGPU] enable few disassembler tests that were mistakenly marked as FIXME.Valery Pykhtin2016-03-311-8/+8
| | | | llvm-svn: 265028
* [PowerPC] Basic support for P9 atomic loads and storesNemanja Ivanovic2016-03-312-0/+19
| | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D18032 This patch provides asm implementation for the following instructions: lwat, ldat, stwat, stdat, ldmx, mcrxrx llvm-svn: 265022
* [AMDGPU] Disassembler: support for DPPSam Kolton2016-03-311-0/+89
| | | | | Review: http://reviews.llvm.org/D18642 llvm-svn: 265015
* [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructionsZlatko Buljan2016-03-312-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D17334 llvm-svn: 265002
* [lanai] Add Lanai backend.Jacques Pienaar2016-03-282-0/+765
| | | | | | | | | | Add the Lanai backend to lib/Target. General Lanai backend discussion on llvm-dev thread "[RFC] Lanai backend" (http://lists.llvm.org/pipermail/llvm-dev/2016-February/095118.html). Differential Revision: http://reviews.llvm.org/D17011 llvm-svn: 264578
* [Power9] Implement new altivec instructions: bcd* seriesChuang-Yu Cheng2016-03-281-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the following altivec instructions: - Decimal Convert From/to National/Zoned/Signed-QWord: bcdcfn. bcdcfz. bcdctn. bcdctz. bcdcfsq. bcdctsq. - Decimal Copy-Sign/Set-Sign: bcdcpsgn. bcdsetsgn. - Decimal Shift/Unsigned-Shift/Shift-and-Round: bcds. bcdus. bcdsr. - Decimal (Unsigned) Truncate: bcdtrunc. bcdutrunc. Total 13 instructions Thanks Amehsan's advice! Thanks Kit's great help! Reviewers: hal, nemanja, kbarton, tjablin, amehsan http://reviews.llvm.org/D17838 llvm-svn: 264568
* [Power9] Implement new vsx instructions: insert, extract, test data class, ↵Chuang-Yu Cheng2016-03-281-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | min/max, reverse, permute, splat This change implements the following vsx instructions: - Scalar Insert/Extract xsiexpdp xsiexpqp xsxexpdp xsxsigdp xsxexpqp xsxsigqp - Vector Insert/Extract xviexpdp xviexpsp xvxexpdp xvxexpsp xvxsigdp xvxsigsp xxextractuw xxinsertw - Scalar/Vector Test Data Class xststdcdp xststdcsp xststdcqp xvtstdcdp xvtstdcsp - Maximum/Minimum xsmaxcdp xsmaxjdp xsmincdp xsminjdp - Vector Byte-Reverse/Permute/Splat xxbrd xxbrh xxbrq xxbrw xxperm xxpermr xxspltib 30 instructions Thanks Nemanja for invaluable discussion! Thanks Kit's great help! Reviewers: hal, nemanja, kbarton, tjablin, amehsan http://reviews.llvm.org/D16842 llvm-svn: 264567
* [Power9] Implement new vsx instructions: quad-precision move, fp-arithmeticChuang-Yu Cheng2016-03-281-0/+66
| | | | | | | | | | | | | | | | | | | | This change implements the following vsx instructions: - quad-precision move xscpsgnqp, xsabsqp, xsnegqp, xsnabsqp - quad-precision fp-arithmetic xsaddqp(o) xsdivqp(o) xsmulqp(o) xssqrtqp(o) xssubqp(o) xsmaddqp(o) xsmsubqp(o) xsnmaddqp(o) xsnmsubqp(o) 22 instructions Thanks Nemanja and Kit for careful review and invaluable discussion! Reviewers: hal, nemanja, kbarton, tjablin, amehsan http://reviews.llvm.org/D16110 llvm-svn: 264565
* [Power9] Implement new altivec instructions: permute, count zero, extend ↵Chuang-Yu Cheng2016-03-261-0/+85
| | | | | | | | | | | | | | | | | | | | | sign, negate, parity, shift/rotate, mul10 This change implements the following vector operations: - vclzlsbb vctzlsbb vctzb vctzd vctzh vctzw - vextsb2w vextsh2w vextsb2d vextsh2d vextsw2d - vnegd vnegw - vprtybd vprtybq vprtybw - vbpermd vpermr - vrlwnm vrlwmi vrldnm vrldmi vslv vsrv - vmul10cuq vmul10uq vmul10ecuq vmul10euq 28 instructions Thanks Nemanja, Kit for invaluable hints and discussion! Reviewers: hal, nemanja, kbarton, tjablin, amehsan Phabricator: http://reviews.llvm.org/D15887 llvm-svn: 264504
* [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, ↵Zlatko Buljan2016-03-241-4/+4
| | | | | | | | DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 llvm-svn: 264248
* [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructionsHrvoje Varga2016-03-242-0/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D17328 llvm-svn: 264246
* [AMDGPU] Fix missing assembler predicates.Valery Pykhtin2016-03-231-0/+236
| | | | | | Differential Revision: http://reviews.llvm.org/D18351 llvm-svn: 264137
* [AMDGPU] add VI disassembler tests. NFC.Valery Pykhtin2016-03-1713-3/+1700
| | | | | | | | Autogenerated from the corresponding assembler tests with a few FIXME added (will fix soon). Differential Revision: http://reviews.llvm.org/D18249 llvm-svn: 263729
* [AMDGPU] Fix VOPC instruction operand namingsValery Pykhtin2016-03-111-0/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D17966 llvm-svn: 263242
* [AMDGPU] Fix SMEM instructions encoding/operand namingsValery Pykhtin2016-03-101-0/+40
| | | | | | Differential Revision: http://reviews.llvm.org/D17651 llvm-svn: 263108
* This change adds co-processor condition branching and conditional traps to ↵Chris Dewhurst2016-03-092-2/+218
| | | | | | | | | | | | | | | | the Sparc back-end. This will allow inline assembler code to utilize these features, but no automatic lowering is provided, except for the previously provided @llvm.trap, which lowers to "ta 5". The change also separates out the different assembly language syntaxes for V8 and V9 Sparc. Previously, only V9 Sparc assembly syntax was provided. The change also corrects the selection order of trap disassembly, allowing, e.g. "ta %g0 + 15" to be rendered, more readably, as "ta 15", ignoring the %g0 register. This is per the sparc v8 and v9 manuals. Check-in includes many extra unit tests to check this works correctly on both V8 and V9 Sparc processors. Code Reviewed at http://reviews.llvm.org/D17960. llvm-svn: 263044
* [Power9] Implement new vsx instructions: load, store instructions for vector ↵Kit Barton2016-03-081-0/+75
| | | | | | | | | | | | | | | | | | | | and scalar We follow the comments mentioned in http://reviews.llvm.org/D16842#344378 to implement this new patch. This patch implements the following vsx instructions: Vector load/store: lxv lxvx lxvb16x lxvl lxvll lxvh8x lxvwsx stxv stxvb16x stxvh8x stxvl stxvll stxvx Scalar load/store: lxsd lxssp lxsibzx lxsihzx stxsd stxssp stxsibx stxsihx 21 instructions Phabricator: http://reviews.llvm.org/D16919 llvm-svn: 262906
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