summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC/Disassembler/Hexagon
Commit message (Collapse)AuthorAgeFilesLines
...
* [Hexagon] Adding word combine dot-new form and replacing old combine opcode.Colin LeMahieu2014-12-091-0/+6
| | | | llvm-svn: 223815
* [Hexagon] Updating predicate register transfers and adding tstbit to allow ↵Colin LeMahieu2014-12-091-0/+4
| | | | | | select selection. Updating ll tests with predicate transfers that previously had nop encodings. llvm-svn: 223800
* [Hexagon] Adding any8, all8, and/or/xor/andn/orn/not predicate register ↵Colin LeMahieu2014-12-082-0/+22
| | | | | | forms, mask, and vitpack instructions and patterns. llvm-svn: 223710
* [Hexagon] Fixing broken test.Colin LeMahieu2014-12-081-1/+1
| | | | llvm-svn: 223704
* [Hexagon] Adding xtype doubleword add, sub, and, or, xor and patterns.Colin LeMahieu2014-12-081-0/+10
| | | | llvm-svn: 223702
* [Hexagon] Adding xtype doubleword comparisons. Removing unused multiclass.Colin LeMahieu2014-12-081-0/+8
| | | | llvm-svn: 223701
* [Hexagon] Adding xtype parity, min, minu, max, maxu instructions.Colin LeMahieu2014-12-082-0/+12
| | | | llvm-svn: 223693
* [Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh/sat/<<16 instructions.Colin LeMahieu2014-12-081-0/+50
| | | | llvm-svn: 223692
* [Hexagon] Adding add/sub with saturation. Removing unused def. Cleaning up ↵Colin LeMahieu2014-12-081-0/+4
| | | | | | shift patterns. llvm-svn: 223680
* [Hexagon] Adding combine reg, reg with predicated forms.Colin LeMahieu2014-12-082-0/+6
| | | | llvm-svn: 223667
* [Hexagon] Adding packhl instruction.Colin LeMahieu2014-12-081-0/+2
| | | | llvm-svn: 223664
* [Hexagon] Adding sub/and/or reg, imm formsColin LeMahieu2014-12-051-0/+6
| | | | llvm-svn: 223522
* [Hexagon] Updating mux_ir/ri/ii/rr with encoding bitsColin LeMahieu2014-12-051-0/+8
| | | | llvm-svn: 223515
* [Hexagon] Adding tfrih/l instructions.Colin LeMahieu2014-12-051-0/+4
| | | | llvm-svn: 223506
* [Hexagon] Adding add reg, imm form with encoding bits and test.Colin LeMahieu2014-12-051-0/+2
| | | | llvm-svn: 223504
* [Hexagon] Adding DoubleRegs decoder. Moving C2_mux and A2_nop. Adding ↵Colin LeMahieu2014-12-051-0/+2
| | | | | | combine imm-imm form. llvm-svn: 223494
* [Hexagon] Adding combine reg-reg forms.Colin LeMahieu2014-12-051-0/+8
| | | | llvm-svn: 223485
* [Hexagon] Marking several instructions as isCodeGenOnly=0 and adding direct ↵Colin LeMahieu2014-12-053-2/+39
| | | | | | disassembly tests for many instructions. llvm-svn: 223482
* [Hexagon] Adding lit exception if Hexagon isn't built.Colin LeMahieu2014-12-041-0/+3
| | | | llvm-svn: 223335
* [Hexagon] Marking some instructions as CodeGenOnly=0 and adding disassembly ↵Colin LeMahieu2014-12-041-0/+18
| | | | | | tests. llvm-svn: 223334
* [Hexagon] Reverting 220584 to address ASAN errors.Colin LeMahieu2014-11-042-7/+0
| | | | llvm-svn: 221210
* [Hexagon] Resubmission of 220427Colin LeMahieu2014-10-242-0/+7
| | | | | | | | | | | Modified library structure to deal with circular dependency between HexagonInstPrinter and HexagonMCInst. Adding encoding bits for add opcode. Adding llvm-mc tests. Removing unit tests. http://reviews.llvm.org/D5624 llvm-svn: 220584
* Revert r220427, "[Hexagon] Adding encoding bits for add opcode."NAKAMURA Takumi2014-10-232-7/+0
| | | | | | It brought cyclic dependecy between HexagonAsmPrinter and HexagonDesc. llvm-svn: 220478
* [Hexagon] Adding encoding bits for add opcode.Colin LeMahieu2014-10-222-0/+7
Adding llvm-mc tests. Removing unit tests. http://reviews.llvm.org/D5624 llvm-svn: 220427
OpenPOWER on IntegriCloud