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| author | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-08 17:33:06 +0000 |
|---|---|---|
| committer | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-08 17:33:06 +0000 |
| commit | b56e6cd9b9bdd0fab494da1d0aa474b8c31c2a73 (patch) | |
| tree | 2fa7a5f56b070d7a9d7041864e26239e4b0a431d /llvm/test/MC/Disassembler/Hexagon | |
| parent | bc0184464141e0022bb2a1d39b20c48f114bdf2b (diff) | |
| download | bcm5719-llvm-b56e6cd9b9bdd0fab494da1d0aa474b8c31c2a73.tar.gz bcm5719-llvm-b56e6cd9b9bdd0fab494da1d0aa474b8c31c2a73.zip | |
[Hexagon] Adding combine reg, reg with predicated forms.
llvm-svn: 223667
Diffstat (limited to 'llvm/test/MC/Disassembler/Hexagon')
| -rw-r--r-- | llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt | 2 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt | 4 |
2 files changed, 6 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt b/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt index 2f1d1b65067..d8952102ec7 100644 --- a/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt +++ b/llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt @@ -10,6 +10,8 @@ # CHECK: r17 = combine(r31.l, r21.l) 0xb0 0xe2 0x0f 0x7c # CHECK: r17:16 = combine(#21, #31) +0x10 0xdf 0x15 0xf5 +# CHECK: r17:16 = combine(r21, r31) 0xf1 0xc3 0x75 0x73 # CHECK: r17 = mux(p3, r21, #31) 0xb1 0xc2 0xff 0x73 diff --git a/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt b/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt index c85b86b5135..c17bd0fdeb9 100644 --- a/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt +++ b/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt @@ -6,6 +6,10 @@ # CHECK: if (p3) r17 = aslh(r21) 0x11 0xe3 0x35 0x70 # CHECK: if (p3) r17 = asrh(r21) +0x70 0xdf 0x15 0xfd +# CHECK: if (p3) r17:16 = combine(r21, r31) +0xf0 0xdf 0x15 0xfd +# CHECK: if (!p3) r17:16 = combine(r21, r31) 0x71 0xdf 0x15 0xf9 # CHECK: if (p3) r17 = and(r21, r31) 0x71 0xdf 0x35 0xf9 |
