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* Remove the cortex-a9-mp CPU.Charlie Turner2014-11-032-2/+2
* [Thumb2] Improve disassembly of memory hintsOliver Stannard2014-10-231-0/+69
* Thumb2 M-class MSR instruction support changesRenato Golin2014-09-012-13/+14
* ARM: implement MRS/MSR (banked reg) system instructions.Tim Northover2014-08-152-0/+303
* Allow only disassembling of M-class MSR masks that the assembler knows how to...James Molloy2014-08-012-4/+125
* ARM: honor hex immediate formatting for ldr/str i12 offsets.Jim Grosbach2014-06-111-0/+6
* llvm-mc: Add option for prefering hex format disassembly.Jim Grosbach2014-06-111-1/+1
* Reduce verbiage of lit.local.cfg filesAlp Toker2014-06-091-2/+1
* ARM: implement support for the UDF mnemonicSaleem Abdulrasool2014-05-141-39/+0
* ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructionsSaleem Abdulrasool2014-01-121-4/+4
* ARM: fix regression caused by r198914Saleem Abdulrasool2014-01-101-0/+12
* [ARM] Add support for MVFR2 which is new in ARMv8Artyom Skrobov2013-11-112-0/+11
* [ARM] Handling for coprocessor instructions that are undefined starting from ...Artyom Skrobov2013-11-082-0/+202
* [ARM] Handling for coprocessor instructions that are undefined starting from ...Artyom Skrobov2013-11-081-0/+167
* [ARM] Handling for coprocessor instructions that are undefined starting from ...Artyom Skrobov2013-11-081-0/+35
* [ARM] NEON instructions were erroneously decoded from certain invalid encodingsArtyom Skrobov2013-10-301-0/+8
* Make ARM hint ranges consistent, and add tests for these rangesArtyom Skrobov2013-10-231-2/+6
* ARM: provide diagnostics on more writeback LDM/STM instructionsTim Northover2013-10-221-0/+16
* Add hint disassembly syntax for 16-bit Thumb hint instructions.Richard Barton2013-10-182-13/+8
* [ARMv8] Add some disassembly tests for Thumb sevl/sevl.wJoey Gouly2013-10-071-0/+5
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-014-11/+7
* Fix spelling intruction -> instruction.Robert Wilhelm2013-09-281-2/+2
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-192-0/+70
* 'svn add' the test cases.Joey Gouly2013-09-182-0/+30
* Fix tests for hasFPARMv8 name change (r190692)Amaury de la Vieuville2013-09-132-2/+2
* [ARMv8] Add some missing tests for DSB/DMB.Joey Gouly2013-09-052-2/+21
* Add AArch32 DCPS{1,2,3} and HLT instructions.Richard Barton2013-09-052-0/+29
* [ARMv8] Add MC support for the new load/store acquire/release instructions.Joey Gouly2013-08-272-0/+65
* [tests] Cleanup initialization of test suffixes.Daniel Dunbar2013-08-161-2/+0
* This fixes the Thumb2 CPS assembly syntax.Mihai Popa2013-08-091-1/+1
* Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.Kevin Enderby2013-07-311-0/+2
* Add not so that these tests pass with pipefail enabled.Rafael Espindola2013-07-233-3/+3
* [ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.Joey Gouly2013-07-192-0/+50
* ARM: delete two tests now integrated into the larger filesTim Northover2013-07-192-19/+0
* ARM: remove invalid invalid testsTim Northover2013-07-192-32/+0
* Improve llvm-mc disassembler mode and refactor ARM tests to use itTim Northover2013-07-1963-611/+972
* [ARMv8] Add NEON instructions VCVT{A, N, P, M}.Joey Gouly2013-07-182-0/+72
* Add Thumb tests for the ARMv8 FP instructions that I recently added.Joey Gouly2013-07-181-0/+163
* Add the tests that I forgot to 'svn add' with my previous commit (r186504).Joey Gouly2013-07-172-0/+20
* Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP.Joey Gouly2013-07-091-0/+24
* Add MC assembly/disassembly support for VRINT{Z, X, R} to V8FP.Joey Gouly2013-07-091-0/+19
* Add MC assembly/disassembly support for VCVT{A, N, P, M} to V8FP.Joey Gouly2013-07-091-0/+49
* Add MC support for the v8fp instructions: vmaxnm and vminnm.Joey Gouly2013-07-061-0/+13
* Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instr...Joey Gouly2013-07-041-0/+25
* Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.Joey Gouly2013-07-042-0/+35
* This corrects the implementation of Thumb ADR instruction. There are three i...Mihai Popa2013-07-031-1/+5
* ARM: operands should be explicit when disassembledAmaury de la Vieuville2013-06-261-0/+4
* ARM: check predicate bits for thumb instructionsAmaury de la Vieuville2013-06-242-0/+18
* ARM: rGPR is meant to be unpredictable, not undefinedAmaury de la Vieuville2013-06-242-3/+2
* ARM: fix thumb1 nop decodingAmaury de la Vieuville2013-06-241-8/+2
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