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* Add support for ARM modified-immediate assembly syntax.Asiri Rathnayake2014-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
* Remove the cortex-a9-mp CPU.Charlie Turner2014-11-031-1/+1
| | | | | | | | | | | | | | | | | | This CPU definition is redundant. The Cortex-A9 is defined as supporting multiprocessing extensions. Remove its definition and update appropriate tests. LLVM defines both a cortex-a9 CPU and a cortex-a9-mp CPU. The only difference between the two CPU definitions in ARM.td is that cortex-a9-mp contains the feature FeatureMP for multiprocessing extensions. This is redundant since the Cortex-A9 is defined as having multiprocessing extensions in the TRMs. armcc also defines the Cortex-A9 as having multiprocessing extensions by default. Change-Id: Ifcadaa6c322be0a33d9d2a39cfdd7da1d75981a7 llvm-svn: 221166
* This reverts r155000.Joey Gouly2013-06-201-4/+0
| | | | | | | | | The cdp2 instruction should have the same restrictions as cdp on the co-processor registers. VFP instructions on v8/AArch32 share the same encoding space as cdp2. llvm-svn: 184445
* ARM: Correct printing of pre-indexed operands.Quentin Colombet2013-04-121-0/+42
| | | | | | | | | | | | | According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
* Specify cpu to unbreak tests.Evan Cheng2012-04-261-1/+1
| | | | llvm-svn: 155604
* Fixed decoding for the ARM cdp2 instruction. The restriction on the ↵Silviu Baranga2012-04-181-0/+3
| | | | | | coprocessor number was removed for this instruction. llvm-svn: 155000
* Added soft fail checks for the disassembler when decoding some corner cases ↵Silviu Baranga2012-03-221-1/+1
| | | | | | of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. llvm-svn: 153252
* ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach2011-11-141-1/+1
| | | | | | | Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. llvm-svn: 144583
* Fix the issue that r143552 was trying to address the _right_ way. ↵Owen Anderson2011-11-021-0/+4
| | | | | | One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. llvm-svn: 143557
* Revert r142618, r142622, and r142624, which were based on an incorrect ↵Owen Anderson2011-10-201-0/+6
| | | | | | reading of the ARMv7 docs. llvm-svn: 142626
* Fix decoding tests for fixed MSR encodings.Owen Anderson2011-10-201-6/+0
| | | | llvm-svn: 142624
* Update test for r141704.Jim Grosbach2011-10-111-3/+3
| | | | llvm-svn: 141705
* Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds ↵James Molloy2011-09-071-1/+1
| | | | | | predicate checking to the Disassembler. llvm-svn: 139250
* STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST ↵Owen Anderson2011-08-181-0/+3
| | | | | | | | for the purposes of decoding all operands except the predicate. Found by randomized testing. llvm-svn: 138003
* Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs ↵Owen Anderson2011-08-181-0/+3
| | | | | | have it unset. llvm-svn: 138000
* Add testcase for STRH. Patch by James Molloy.Owen Anderson2011-08-151-0/+3
| | | | llvm-svn: 137644
* Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.Owen Anderson2011-08-111-0/+3
| | | | llvm-svn: 137347
* Correct immediate range for shifter operands. Patch by James Molloy, with ↵Owen Anderson2011-08-111-0/+3
| | | | | | additional encoding fixes added by me. llvm-svn: 137322
* ARM Disassembler: sign extend branch immediates.Benjamin Kramer2011-08-091-0/+3
| | | | | | Not sure about BLXi, but this is what the old disassembler did. llvm-svn: 137156
* Replace the existing ARM disassembler with a new one based on the ↵Owen Anderson2011-08-091-3/+6
| | | | | | | | | | FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-031-2/+5
| | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
* ARM SRS instruction parsing, diassembly and encoding support.Jim Grosbach2011-07-291-0/+6
| | | | | | | | Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. llvm-svn: 136509
* Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach2011-07-191-2/+2
| | | | | | | | The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. llvm-svn: 135532
* Simplify printing of ARM shifted immediates.Jim Grosbach2011-07-111-4/+4
| | | | | | | | | Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902
* Fix Bug 9386 - ARM disassembler failed to disassemble conditional bxJohnny Chen2011-05-221-0/+3
| | | | | | | Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and modified ARMDisassemblerCore.cpp a little bit. llvm-svn: 131859
* Add tests for A8.6.110 NOP.Johnny Chen2011-04-271-0/+3
| | | | llvm-svn: 130345
* Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.Johnny Chen2011-04-081-0/+3
| | | | | | | PR9650 rdar://problem/9257565 llvm-svn: 129147
* MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it.Johnny Chen2011-04-081-0/+6
| | | | | | Add tests for that. llvm-svn: 129137
* Add sanity checking for bad register specifier(s) for the DPFrm instructions.Johnny Chen2011-04-081-0/+18
| | | | | | Add more test cases to exercise the logical branches related to the above change. llvm-svn: 129117
* Add sanity checking for invalid register encodings for signed/unsigned ↵Johnny Chen2011-04-071-0/+6
| | | | | | | | extend instructions. Add some test cases. llvm-svn: 129098
* Add some more comments about checkings of invalid register numbers.Johnny Chen2011-04-071-0/+3
| | | | | | And two test cases. llvm-svn: 129090
* Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.Johnny Chen2011-04-061-1/+4
| | | | | | | | | | Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25}) is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid. rdar://problem/9239347 rdar://problem/9239467 llvm-svn: 128977
* Fix a typo in the handling of PKHTB opcode, plus add sanity check for ↵Johnny Chen2011-04-051-3/+6
| | | | | | | | | | illegal register encodings for DisassembleArithMiscFrm(). rdar://problem/9238659 llvm-svn: 128958
* The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.Johnny Chen2011-04-051-0/+3
| | | | | | | | Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change. rdar://problem/9236873 llvm-svn: 128922
* LDRD now prints out two dst registers.Johnny Chen2011-04-051-1/+1
| | | | llvm-svn: 128909
* Constants with multiple encodings (ARM):Johnny Chen2011-04-051-3/+3
| | | | | | | | | | An alternative syntax is available for a modified immediate constant that permits the programmer to specify the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where: <byte> is the numeric value of abcdefgh, in the range 0-255 <rot> is twice the numeric value of rotation, an even number in the range 0-30. llvm-svn: 128897
* Fixed a bug in disassembly of STR_POST, where the immediate is the second ↵Johnny Chen2011-04-021-0/+3
| | | | | | | | | | operand in am2offset; instead of the second operand in addrmode_imm12. rdar://problem/9225289 llvm-svn: 128757
* Fix the instruction table entries for AI1_adde_sube_s_irs multiclass ↵Johnny Chen2011-04-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | definition so that all the instruction have: let Inst{31-27} = 0b1110; // non-predicated Before, the ARM decoder was confusing: > 0x40 0xf3 0xb8 0x80 as: Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcs pc, r8, r0, asr #6 since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'. Now, the AR decoder behaves correctly: > 0x40 0xf3 0xb8 0x80 > END Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcshi pc, r8, r0, asr #6 > rdar://problem/9223094 llvm-svn: 128746
* Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we ↵Johnny Chen2011-04-011-0/+3
| | | | | | | | should reject the instruction as invalid. llvm-svn: 128734
* Fix LDRi12 immediate operand, which was changed to be the second operand in ↵Johnny Chen2011-04-011-0/+9
| | | | | | | | $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). rdar://problem/9219356 llvm-svn: 128722
* Add BLXi to the instruction table for disassembly purpose.Johnny Chen2011-03-311-0/+3
| | | | | | | | A8.6.23 BLX (immediate) rdar://problem/9212921 llvm-svn: 128644
* Add a test case for MSRi.Johnny Chen2011-03-291-0/+3
| | | | llvm-svn: 128494
* A8.6.188 STC, STC2Johnny Chen2011-03-291-0/+6
| | | | | | | | The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}. rdar://problem/9200661 llvm-svn: 128478
* Add and modify some tests.Johnny Chen2011-03-291-0/+6
| | | | llvm-svn: 128476
* Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't ↵Owen Anderson2011-03-291-3/+0
| | | | | | actually exist. llvm-svn: 128461
* Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add ↵Johnny Chen2011-03-281-0/+9
| | | | | | | | some test cases. Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly. llvm-svn: 128417
* Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt.Johnny Chen2011-03-251-0/+3
| | | | llvm-svn: 128306
* Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. ↵Johnny Chen2011-03-251-0/+3
| | | | | | | | Modify the disassembler to handle that. rdar://problem/9184053 llvm-svn: 128285
* ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder ↵Johnny Chen2011-03-241-0/+3
| | | | | | | | | was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. llvm-svn: 128234
* Load/Store Multiple:Johnny Chen2011-03-241-0/+6
| | | | | | | These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add two test cases. llvm-svn: 128191
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