summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC/Disassembler/AMDGPU
Commit message (Collapse)AuthorAgeFilesLines
...
* [AMDGPU][MC] Removed V_MQSAD_U16_U8Dmitry Preobrazhensky2017-05-151-0/+18
| | | | | | | | | | | | This instruction does not really exist See Bug 33018: https://bugs.llvm.org//show_bug.cgi?id=33018 Reviewers: vpykhtin, artem.tamazov Differential Revision: https://reviews.llvm.org/D33126 llvm-svn: 303055
* AMDGPU: Remove tfe bit from flat instruction definitionsMatt Arsenault2017-05-111-24/+0
| | | | | | | | | | We don't use it and it was removed in gfx9, and the encoding bit repurposed. Additionally actually using it requires changing the output register class, which wasn't done anyway. llvm-svn: 302814
* [AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in ↵Dmitry Preobrazhensky2017-05-102-7/+7
| | | | | | | | | | | | disassembler output See bug 32927: https://bugs.llvm.org//show_bug.cgi?id=32927 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D32913 llvm-svn: 302648
* [AMDGPU][mc][tests][NFC] Bulk ISA tests: update for Gfx7/Gfx8, add for Gfx9.Artem Tamazov2017-04-241-57799/+65599
| | | | llvm-svn: 301247
* [AMDGPU][MC] Corrected src0 size for s_cbranch_joinDmitry Preobrazhensky2017-04-121-1/+1
| | | | | | | | | | Fix for bug 28159: https://bugs.llvm.org//show_bug.cgi?id=28159 Reviewers: vpykhtin, arsenm Differential Revision: https://reviews.llvm.org/D31595 llvm-svn: 300055
* AMDGPU: Fix crash when disassembling VOP3 macMatt Arsenault2017-04-101-0/+19
| | | | | | | | | | | | The unused dummy src2_modifiers is missing, so it crashes when trying to print it. I tried to fully remove src2_modifiers, but there are some irritations in the places where it is converted to mad since it starts to require modifying use lists while iterating over them. llvm-svn: 299861
* [AMDGPU][MC] Fix for Bug 28211 + LIT testsDmitry Preobrazhensky2017-04-071-10/+16
| | | | | | | | | | | | | | | | | | | | - corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description) - address operand is not used - several opcodes have data operand - all opcodes have offset modifier - DS_AND_SRC2_B32: corrected typo in mnemo - DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32 - added CI/VI opcodes: - DS_CONDXCHG32_RTN_B64 - DS_GWS_SEMA_RELEASE_ALL - added VI opcodes: - DS_CONSUME - DS_APPEND - DS_ORDERED_COUNT Differential Revision: https://reviews.llvm.org/D31707 llvm-svn: 299767
* [AMDGPU][MC] Fix for Bugs 28200, 28202 + LIT testsDmitry Preobrazhensky2017-03-201-0/+6
| | | | | | | | | | Fixed several related issues with VOP3 fp modifiers. Reviewers: artem.tamazov Differential Revision: https://reviews.llvm.org/D30821 llvm-svn: 298255
* AMDGPU: Add definition for v_swap_b32Matt Arsenault2017-02-281-0/+4
| | | | | | | | This is somewhat tricky because there are two pairs of tied operands, and it isn't allowed to be VOP3 encoded. llvm-svn: 296519
* AMDGPU: Fix disassembly of aperture registersMatt Arsenault2017-02-181-0/+13
| | | | llvm-svn: 295555
* AMDGPU: Replace assert with report_fatal_errorMatt Arsenault2017-02-151-0/+4
| | | | | | Also use a more refined condition. llvm-svn: 295239
* Reapply [AMDGPU][mc][tests][NFC] Add coverage/smoke tests for Gfx7 and Gfx8.Artem Tamazov2017-01-301-0/+87676
| | | | llvm-svn: 293552
* Revert [AMDGPU][mc][tests][NFC] Add coverage/smoke tests for Gfx7 and Gfx8.Ivan Krasin2017-01-241-87676/+0
| | | | | | | | | | | | Reason: broke ASAN bots with a global buffer overflow. http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/2291 Each test contains 20-30K test cases but takes only several (from 4 to 10) seconds to complete on average machine. The tests cover the majority of AMDGPU Gfx7/Gfx8 instructions, including many dark corners, and intended to quickly find out if something is broken. llvm-svn: 292974
* [AMDGPU][mc][tests][NFC] Add coverage/smoke tests for Gfx7 and Gfx8.Artem Tamazov2017-01-241-0/+87676
| | | | | | | | | Each test contains 20-30K test cases but takes only several (from 4 to 10) seconds to complete on average machine. The tests cover the majority of AMDGPU Gfx7/Gfx8 instructions, including many dark corners, and intended to quickly find out if something is broken. llvm-svn: 292922
* [AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwaSam Kolton2016-12-222-3/+11
| | | | | | | | | | | | Summary: Real instruction should copy constraints from real instruction. This allows auto-generated disassembler to correctly process tied operands. Reviewers: nhaustov, vpykhtin, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D27847 llvm-svn: 290336
* AMDGPU: Fix name for v_ashrrev_i16Matt Arsenault2016-12-162-2/+2
| | | | llvm-svn: 289967
* AMDGPU: Change vintrp printingMatt Arsenault2016-12-141-16/+16
| | | | llvm-svn: 289664
* AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault2016-12-102-2/+56
| | | | | | | | | | | | | | | | | | Since 32-bit instructions with 32-bit input immediate behavior are used to materialize 16-bit constants in 32-bit registers for 16-bit instructions, determining the legality based on the size is incorrect. Change operands to have the size specified in the type. Also adds a workaround for a disassembler bug that produces an immediate MCOperand for an operand that is supposed to be OPERAND_REGISTER. The assembler appears to accept out of bounds immediates and truncates them, but this seems to be an issue for 32-bit already. llvm-svn: 289306
* AMDGPU: Fix vintrp disassemblyMatt Arsenault2016-12-102-5/+49
| | | | llvm-svn: 289292
* AMDGPU: Change vintrp printing to better match scMatt Arsenault2016-12-101-1/+1
| | | | | | | Some of the immediates need to be printed differently eventually. llvm-svn: 289291
* AMDGPU: Fix operand name for v_interp_*Matt Arsenault2016-12-061-1/+1
| | | | | | Other VOP instructions call the output vdst llvm-svn: 288856
* [AMDGPU] Disassembler: fix s_buffer_store_dword instructionsSam Kolton2016-12-051-0/+36
| | | | | | | | | | | | Summary: s_buffer_store_dword instructions sdata operand was called sdst in encoding. This caused disassembler to fail. Reviewers: tstellarAMD, vpykhtin, artem.tamazov Subscribers: arsenm, nhaehnle, rampitec Differential Revision: https://reviews.llvm.org/D27100 llvm-svn: 288657
* [AMDGPU] Add f16 support (VI+)Konstantin Zhuravlyov2016-11-131-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D25975 llvm-svn: 286753
* [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.Artem Tamazov2016-10-311-0/+3
| | | | | | | | | | | Fixes Bug 30808. Note that passing subtarget information to predicates seems too complicated, so gfx8-specific def smrd_offset_20 introduced. Old gfx6/7-specific def renamed to smrd_offset_8 for clarity. Lit tests updated. Differential Revision: https://reviews.llvm.org/D26085 llvm-svn: 285590
* [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.Artem Tamazov2016-10-211-8/+8
| | | | | | | | Fixes Bug 28215. Lit tests updated. Differential Revision: https://reviews.llvm.org/D25837 llvm-svn: 284825
* [AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_store_dwordx3.Artem Tamazov2016-10-071-0/+6
| | | | | | | | | Partially fixes Bug 28232. Lit tests added. Differential Revision: https://reviews.llvm.org/D25367 llvm-svn: 283567
* [AMDGPU] fix failure on printing of non-existing instruction operands.Valery Pykhtin2016-08-151-0/+5
| | | | | | Differential revision: https://reviews.llvm.org/D23323 llvm-svn: 278665
* Revert "[AMDGPU] fix failure on printing of non-existing instruction operands."Valery Pykhtin2016-08-111-5/+0
| | | | | | This reverts revision 278333, newly added test failed. llvm-svn: 278336
* [AMDGPU] fix failure on printing of non-existing instruction operands.Valery Pykhtin2016-08-111-0/+5
| | | | | | Differential revision: https://reviews.llvm.org/D23323 llvm-svn: 278333
* [AMDGPU] refactor DS instruction definitions. NFC.Valery Pykhtin2016-08-011-9/+0
| | | | | | Differential revision: https://reviews.llvm.org/D22522 llvm-svn: 277344
* [AMDGPU] fix ds_swizzle_b32 opcode for VI (bz 28371)Valery Pykhtin2016-07-081-2/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D22049 llvm-svn: 274852
* [AMDGPU] Disassembler: Support for sdwa instructionsSam Kolton2016-06-091-0/+347
| | | | | | | | | | Reviewers: vpykhtin, tstellarAMD Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D21129 llvm-svn: 272255
* [AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when ↵Artem Tamazov2016-06-062-0/+6
| | | | | | | | | | | | src2 == VCC. Another step for unification llvm assembler/disassembler with sp3. Besides, CodeGen output is a bit improved, thus changes in CodeGen tests. Assembler/Disassembler tests updated/added. Differential Revision: http://reviews.llvm.org/D20796 llvm-svn: 271900
* [AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers.Artem Tamazov2016-05-241-0/+109
| | | | | | Differential Revision: http://reviews.llvm.org/D20476 llvm-svn: 270552
* [AMDGPU][llvm-mc] Fixes to support buffer atomics.Artem Tamazov2016-05-191-0/+119
| | | | | | | | | | | | Fixes for MUBUF_Atomic instructions to make operand list valid: - For RTN insns, make a copy of $vdata_in operand as $vdata. - Do not add operand for GLC, it is hardcoded and comes as a token. Workaround to avoid adding multiple default optional operands. Tests added. Differential Revision: http://reviews.llvm.org/D20257 llvm-svn: 270049
* [AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.Artem Tamazov2016-05-061-2/+32
| | | | | | | | | | | | | | | | | | | Added support for sendmsg(MSG[, OP[, STREAM_ID]]) syntax in s_sendmsg and s_sendmsghalt instructions. The syntax matches the SP3 assembler/disassembler rules. That is why implicit inputs (like M0 and EXEC) are not printed to disassembly output anymore. sendmsg(...) allows only known message types and attributes, even if literals are used instead of symbolic names. However, raw literal (without "sendmsg") still can be used, and that allows for any 16-bit value. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19596 llvm-svn: 268762
* AMDGPU/SI: Assembler: Unify parsing/printing of operands.Nikolay Haustov2016-04-291-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The goal is for each operand type to have its own parse function and at the same time share common code for tracking state as different instruction types share operand types (e.g. glc/glc_flat, etc). Introduce parseAMDGPUOperand which can parse any optional operand. DPP and Clamp/OMod have custom handling for now. Sam also suggested to have class hierarchy for operand types instead of table. This can be done in separate change. Remove parseVOP3OptionalOps, parseDS*OptionalOps, parseFlatOptionalOps, parseMubufOptionalOps, parseDPPOptionalOps. Reduce number of definitions of AsmOperand's and MatchClasses' by using common base class. Rename AsmMatcher/InstPrinter methods accordingly. Print immediate type when printing parsed immediate operand. Use 'off' if offset/index register is unused instead of skipping it to make it more readable (also agreed with SP3). Update tests. Reviewers: tstellarAMD, SamWot, artem.tamazov Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19584 llvm-svn: 268015
* [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware ↵Artem Tamazov2016-04-271-3/+9
| | | | | | | | | | | | registers. Possibility to specify code of hardware register kept. Disassemble to symbolic name, if name is known. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19335 llvm-svn: 267724
* [AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax.Artem Tamazov2016-04-251-5/+5
| | | | | | | | | | | | | Added hwreg(reg[,offset,width]) syntax. Default offset = 0, default width = 32. Possibility to specify 16-bit immediate kept. Added out-of-range checks. Disassembling is always to hwreg(...) format. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19329 llvm-svn: 267410
* [AMDGPU][llvm-mc] s_setreg* - Fix order of operandsArtem Tamazov2016-04-181-2/+2
| | | | | | | | Order should match the sp3 syntax, where destination (simm16 denoting the hwreg) is coming first. Differential Revision: http://reviews.llvm.org/D19161 llvm-svn: 266617
* [AMDGPU] Add some VI disassembler tests missing from previous autogeneration ↵Valery Pykhtin2016-04-081-0/+66
| | | | | | due to different filecheck prefix. NFC. llvm-svn: 265769
* [AMDGPU] fix readlane/readfirstlane src vgpr operand type.Valery Pykhtin2016-04-072-2/+5
| | | | | | | | | For VGPR_32 operand disassembler expects a VGPR register encoded as 0..255 (enum8 src operand). readfirstlane/readline actually has enum9 operand and this change fixes VGPR_32 to VS_32 (enum9 encoding). Differential Revision: http://reviews.llvm.org/D18696 llvm-svn: 265670
* [AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields.Valery Pykhtin2016-04-011-8/+8
| | | | | | | | $vsrc1 -> $src1, $k -> $imm Differential Revision: http://reviews.llvm.org/D18659 llvm-svn: 265141
* [AMDGPU] enable few disassembler tests that were mistakenly marked as FIXME.Valery Pykhtin2016-03-311-8/+8
| | | | llvm-svn: 265028
* [AMDGPU] Disassembler: support for DPPSam Kolton2016-03-311-0/+89
| | | | | Review: http://reviews.llvm.org/D18642 llvm-svn: 265015
* [AMDGPU] Fix missing assembler predicates.Valery Pykhtin2016-03-231-0/+236
| | | | | | Differential Revision: http://reviews.llvm.org/D18351 llvm-svn: 264137
* [AMDGPU] add VI disassembler tests. NFC.Valery Pykhtin2016-03-1713-3/+1700
| | | | | | | | Autogenerated from the corresponding assembler tests with a few FIXME added (will fix soon). Differential Revision: http://reviews.llvm.org/D18249 llvm-svn: 263729
* [AMDGPU] Fix VOPC instruction operand namingsValery Pykhtin2016-03-111-0/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D17966 llvm-svn: 263242
* [AMDGPU] Fix SMEM instructions encoding/operand namingsValery Pykhtin2016-03-101-0/+40
| | | | | | Differential Revision: http://reviews.llvm.org/D17651 llvm-svn: 263108
* [AMDGPU] Disassembler: Support for all VOP1 instructions.Nikolay Haustov2016-02-251-0/+250
| | | | | | | | | | | | | | | Support all instructions with VOP1 encoding with 32 or 64-bit operands for VI subtarget: VGPR_32 and VReg_64 operand register classes VS_32 and VS_64 operand register classes with inline and literal constants Tests for VOP1 instructions. Patch by: skolton Reviewers: arsenm, tstellarAMD Review: http://reviews.llvm.org/D17194 llvm-svn: 261878
OpenPOWER on IntegriCloud