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| author | Artem Tamazov <artem.tamazov@amd.com> | 2016-10-31 16:07:39 +0000 |
|---|---|---|
| committer | Artem Tamazov <artem.tamazov@amd.com> | 2016-10-31 16:07:39 +0000 |
| commit | 54bfd548aa139a331d1c3fdff691c70dfd409986 (patch) | |
| tree | 9fc48b1eb44e8c1c7baa8d2d173f855bc883be3d /llvm/test/MC/Disassembler/AMDGPU | |
| parent | 54c5a545bebb088c31d17ed0fba053ecd104e0cd (diff) | |
| download | bcm5719-llvm-54bfd548aa139a331d1c3fdff691c70dfd409986.tar.gz bcm5719-llvm-54bfd548aa139a331d1c3fdff691c70dfd409986.zip | |
[AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.
Fixes Bug 30808.
Note that passing subtarget information to predicates seems too complicated, so gfx8-specific def smrd_offset_20 introduced.
Old gfx6/7-specific def renamed to smrd_offset_8 for clarity.
Lit tests updated.
Differential Revision: https://reviews.llvm.org/D26085
llvm-svn: 285590
Diffstat (limited to 'llvm/test/MC/Disassembler/AMDGPU')
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/smrd_vi.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/AMDGPU/smrd_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/smrd_vi.txt index 8191bd1845e..630c55f6b55 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/smrd_vi.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/smrd_vi.txt @@ -9,6 +9,9 @@ # VI: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x41,0x00,0x02,0xc0,0x01,0x00,0x00,0x00] 0x41 0x00 0x02 0xc0 0x01 0x00 0x00 0x00 +# VI: s_load_dword s1, s[2:3], 0xfffff ; encoding: [0x41,0x00,0x02,0xc0,0xff,0xff,0x0f,0x00] +0x41,0x00,0x02,0xc0,0xff,0xff,0x0f,0x00 + # VI: s_load_dword s1, s[2:3], s4 ; encoding: [0x41,0x00,0x00,0xc0,0x04,0x00,0x00,0x00] 0x41 0x00 0x00 0xc0 0x04 0x00 0x00 0x00 |
