summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC/Disassembler/AMDGPU
Commit message (Expand)AuthorAgeFilesLines
* AMDGPU: Fix operand name for v_interp_*Matt Arsenault2016-12-061-1/+1
* [AMDGPU] Disassembler: fix s_buffer_store_dword instructionsSam Kolton2016-12-051-0/+36
* [AMDGPU] Add f16 support (VI+)Konstantin Zhuravlyov2016-11-131-2/+2
* [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.Artem Tamazov2016-10-311-0/+3
* [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.Artem Tamazov2016-10-211-8/+8
* [AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_store_dwordx3.Artem Tamazov2016-10-071-0/+6
* [AMDGPU] fix failure on printing of non-existing instruction operands.Valery Pykhtin2016-08-151-0/+5
* Revert "[AMDGPU] fix failure on printing of non-existing instruction operands."Valery Pykhtin2016-08-111-5/+0
* [AMDGPU] fix failure on printing of non-existing instruction operands.Valery Pykhtin2016-08-111-0/+5
* [AMDGPU] refactor DS instruction definitions. NFC.Valery Pykhtin2016-08-011-9/+0
* [AMDGPU] fix ds_swizzle_b32 opcode for VI (bz 28371)Valery Pykhtin2016-07-081-2/+2
* [AMDGPU] Disassembler: Support for sdwa instructionsSam Kolton2016-06-091-0/+347
* [AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when ...Artem Tamazov2016-06-062-0/+6
* [AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers.Artem Tamazov2016-05-241-0/+109
* [AMDGPU][llvm-mc] Fixes to support buffer atomics.Artem Tamazov2016-05-191-0/+119
* [AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.Artem Tamazov2016-05-061-2/+32
* AMDGPU/SI: Assembler: Unify parsing/printing of operands.Nikolay Haustov2016-04-291-34/+34
* [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware regis...Artem Tamazov2016-04-271-3/+9
* [AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax.Artem Tamazov2016-04-251-5/+5
* [AMDGPU][llvm-mc] s_setreg* - Fix order of operandsArtem Tamazov2016-04-181-2/+2
* [AMDGPU] Add some VI disassembler tests missing from previous autogeneration ...Valery Pykhtin2016-04-081-0/+66
* [AMDGPU] fix readlane/readfirstlane src vgpr operand type.Valery Pykhtin2016-04-072-2/+5
* [AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields.Valery Pykhtin2016-04-011-8/+8
* [AMDGPU] enable few disassembler tests that were mistakenly marked as FIXME.Valery Pykhtin2016-03-311-8/+8
* [AMDGPU] Disassembler: support for DPPSam Kolton2016-03-311-0/+89
* [AMDGPU] Fix missing assembler predicates.Valery Pykhtin2016-03-231-0/+236
* [AMDGPU] add VI disassembler tests. NFC.Valery Pykhtin2016-03-1713-3/+1700
* [AMDGPU] Fix VOPC instruction operand namingsValery Pykhtin2016-03-111-0/+25
* [AMDGPU] Fix SMEM instructions encoding/operand namingsValery Pykhtin2016-03-101-0/+40
* [AMDGPU] Disassembler: Support for all VOP1 instructions.Nikolay Haustov2016-02-251-0/+250
* [AMDGPU] Disassembler: Added basic disassembler for AMDGPU targetTom Stellard2016-02-183-0/+37
OpenPOWER on IntegriCloud