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* [ARM] Add B.W and CBZ instructions to ARMv8-M BaselineBradley Smith2016-01-152-0/+22
| | | | llvm-svn: 257881
* [ARM] Add SDIV/UDIV instructions to ARMv8-M BaselineBradley Smith2016-01-151-0/+8
| | | | llvm-svn: 257880
* [ARM] Add MOVW/MOVT instructions to ARMv8-M Baseline/MainlineBradley Smith2016-01-152-0/+35
| | | | llvm-svn: 257879
* [ARM] Add ARMv8-M Baseline/Mainline LLVM targetingBradley Smith2016-01-151-0/+22
| | | | llvm-svn: 257878
* [ARM] Split out ARMv8-A semaphores and atomics and ARMv7 clrex as separate ↵Bradley Smith2016-01-153-30/+30
| | | | | | features llvm-svn: 257877
* [ARM] Fix several state persistence bugsKeno Fischer2016-01-121-0/+9
| | | | | | | | | | | | | | | | | | | | | | | Summary: This fixes three bugs, in all of which state is not or incorrecly reset between objects (i.e. when reusing the same pass manager to create multiple object files): 1) AttributeSection needs to be reset to nullptr, because otherwise the backend will try to emit into the old object file's attribute section causing a segmentation fault. 2) MappingSymbolCounter needs to be reset, otherwise the second object file will start where the first one left off. 3) The MCStreamer base class resets the Streamer's e_flags settings. Since EF_ARM_EABI_VER5 is set on streamer creation, we need to set it again after the MCStreamer was rest. Also rename Reset (uppser case) to EHReset to avoid confusion with reset (lower case). Reviewers: rengolin Differential Revision: http://reviews.llvm.org/D15950 llvm-svn: 257473
* Fix several accidental DOS line endings in source filesDimitry Andric2016-01-031-7/+7
| | | | | | | | | | | | | | | Summary: There are a number of files in the tree which have been accidentally checked in with DOS line endings. Convert these to native line endings. There are also a few files which have DOS line endings on purpose, and I have set the svn:eol-style property to 'CRLF' on those. Reviewers: joerg, aaron.ballman Subscribers: aaron.ballman, sanjoy, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15848 llvm-svn: 256707
* Support clrex instruction on ARMv6k. Patch by Andrew Turner.Roman Divacky2015-12-281-5/+18
| | | | llvm-svn: 256505
* Form reform for MCDwarf.Paul Robinson2015-12-234-13/+18
| | | | | | | | | MCDwarf emits a canned abbreviation table, but was not emitting proper forms for DWARF version 4, which is the default after r249655. Differential Revision: http://reviews.llvm.org/D15732 llvm-svn: 256313
* [MC, COFF] Support link /incremental conditionallyDavid Majnemer2015-12-211-1/+1
| | | | | | | | | | | | | | | | Today, we always take into account the possibility that object files produced by MC may be consumed by an incremental linker. This results in us initialing fields which vary with time (TimeDateStamp) which harms hermetic builds (e.g. verifying a self-host went well) and produces sub-optimal code because we cannot assume anything about the relative position of functions within a section (call sites can get redirected through incremental linker thunks). Let's provide an MCTargetOption which controls this behavior so that we can disable this functionality if we know a-priori that the build will not rely on /incremental. llvm-svn: 256203
* Avoid explicit relocation sorting most of the time.Rafael Espindola2015-12-175-12/+12
| | | | | | | | | | These days relocations are created and stored in a deterministic way. The order they are created is also suitable for the .o file, so we don't need an explicit sort. The last remaining exception is MIPS. llvm-svn: 255902
* Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions"Reid Kleckner2015-12-162-446/+0
| | | | | | This reverts commit r255762. llvm-svn: 255806
* [ARM] Add ARMv8.2-A FP16 vector instructionsOliver Stannard2015-12-162-0/+693
| | | | | | | | | | | | | | ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. Differential Revision: http://reviews.llvm.org/D15039 llvm-svn: 255764
* [ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2015-12-162-0/+446
| | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 llvm-svn: 255762
* [ARM] Allowing SP/PC for AND/BIC mod_imm_notRenato Golin2015-12-081-0/+11
| | | | | | | AND/BIC instructions do accept SP/PC, so the register class should be more generic (rGPR -> GPR) to cope with that case. Adding more tests. llvm-svn: 255034
* [ARM] Generate ABI_optimization_goals build attribute, as described in the ↵Artyom Skrobov2015-12-071-8/+8
| | | | | | | | | | | | | | ARM ARM. Summary: This reverts r254234, and adds a simple fix for the annoying case of use-after-free. Reviewers: rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D15236 llvm-svn: 254912
* [ARM] Flag vcvt{t,b} with an f16 type specifier as part of the FP16 extensionBradley Smith2015-12-071-0/+18
| | | | | | Additionally correct the Cortex-R7 definition to allow the FP16 feature. llvm-svn: 254900
* [ARM] Add ARMv8.2-A to TargetParserOliver Stannard2015-12-011-0/+46
| | | | | | | | | | | | Add ARMv8.2-A to TargetParser, so that it can be used by the clang command-line options and the .arch directive. Most testing of this will be done in clang, checking that the command-line options that this enables work. Differential Revision: http://reviews.llvm.org/D15037 llvm-svn: 254400
* Revert "[ARM] Generate ABI_optimization_goals build attribute, as described ↵Renato Golin2015-11-281-8/+8
| | | | | | | | | in the ARM ARM." This reverts commit r254201 and r254202, as it broke test-suite, self-hosting and sanitizer tests on ARM buildbots. llvm-svn: 254234
* [ARM] Generate ABI_optimization_goals build attribute, as described in the ↵Artyom Skrobov2015-11-271-8/+8
| | | | | | | | | | | | | | | | | | | ARM ARM. Summary: Since this build attribute corresponds to a whole module, and different functions in a module may differ in the optimizations enabled for them, this attribute is emitted after all functions, and only in the case that the optimization goals for all functions match. Reviewers: logan, hans Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14934 llvm-svn: 254201
* Handle ARMv6-J as an alias, instead of fake architectureArtyom Skrobov2015-11-201-34/+0
| | | | | | | | | | | | | | | | | | | | | | Summary: This follows D14577 to treat ARMv6-J as an alias for ARMv6, instead of an architecture in its own right. The functional change is that the default CPU when targeting ARMv6-J changes from arm1136j-s to arm1136jf-s, which is currently used as the default CPU for ARMv6; both are, in fact, ARMv6-J CPUs. The J-bit (Jazelle support) is irrelevant to LLVM, and it doesn't affect code generation, attributes, optimizations, or anything else, apart from selecting the default CPU. Reviewers: rengolin, logan, compnerd Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14755 llvm-svn: 253675
* [Assembler] Make fatal assembler errors non-fatalOliver Stannard2015-11-179-68/+93
| | | | | | | | | | | | | | Currently, if the assembler encounters an error after parsing (such as an out-of-range fixup), it reports this as a fatal error, and so stops after the first error. However, for most of these there is an obvious way to recover after emitting the error, such as emitting the fixup with a value of zero. This means that we can report on all of the errors in a file, not just the first one. MCContext::reportError records the fact that an error was encountered, so we won't actually emit an object file with the incorrect contents. Differential Revision: http://reviews.llvm.org/D14717 llvm-svn: 253328
* [ARM,AArch64] Store source location of asm constant pool entriesOliver Stannard2015-11-161-0/+5
| | | | | | | | | | Storing the source location of the expression that created a constant pool entry allows us to emit better error messages if we later discover that the expression cannot be represented by a relocation. Differential Revision: http://reviews.llvm.org/D14646 llvm-svn: 253220
* [ARM,AArch64] Store source location for values in assembly filesOliver Stannard2015-11-161-0/+5
| | | | | | | | | | | The MCValue class can store a SMLoc to allow better error messages to be emitted if an error is detected after parsing. The ARM and AArch64 assembly parsers were not setting this, so error messages did not have source information. Differential Revision: http://reviews.llvm.org/D14645 llvm-svn: 253219
* Handle ARMv6KZ namingArtyom Skrobov2015-11-162-40/+2
| | | | | | | | | | | | | | | | | | | | | | | Summary: * ARMv6KZ is the "canonical" name, given in the ARMARM * ARMv6Z is an "official abbreviation" for it, mentioned in the ARMARM * ARMv6ZK is a popular misspelling, which we should support as an alias. The patch corrects the handling of the names. Functional changes: * ARMv6Z no longer treated as an architecture in its own right * ARMv6ZK renamed to ARMv6KZ, accepting ARMv6ZK as an alias * arm1176jz-s and arm1176jzf-s recognized as ARMv6ZK, instead of ARMv6K * default ARMv6K CPU changed to arm1176j-s Reviewers: rengolin, logan, compnerd Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14568 llvm-svn: 253206
* DI: Reverse direction of subprogram -> function edge.Peter Collingbourne2015-11-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Previously, subprograms contained a metadata reference to the function they described. Because most clients need to get or set a subprogram for a given function rather than the other way around, this created unneeded inefficiency. For example, many passes needed to call the function llvm::makeSubprogramMap() to build a mapping from functions to subprograms, and the IR linker needed to fix up function references in a way that caused quadratic complexity in the IR linking phase of LTO. This change reverses the direction of the edge by storing the subprogram as function-level metadata and removing DISubprogram's function field. Since this is an IR change, a bitcode upgrade has been provided. Fixes PR23367. An upgrade script for textual IR for out-of-tree clients is attached to the PR. Differential Revision: http://reviews.llvm.org/D14265 llvm-svn: 252219
* Go back to producing relocations for out of range symbols.Rafael Espindola2015-11-052-7/+5
| | | | | | | | This brings back the behavior from before r252090 for out of range symbols. Should bring some arm bots back. llvm-svn: 252119
* Slightly saner handling of thumb branches.Rafael Espindola2015-11-042-0/+27
| | | | | | | | The generic infrastructure already did a lot of work to decide if the fixup value is know or not. It doesn't make sense to reimplement a very basic case: same fragment. llvm-svn: 252090
* Don't create empty sections just to look like gas.Rafael Espindola2015-11-034-20/+20
| | | | | | | We are long past the time when this much bug for bug compatibility was useful. llvm-svn: 251970
* WatchOS: update default CPU for triple after t2dsp -> dsp renameTim Northover2015-11-021-0/+4
| | | | llvm-svn: 251814
* Recognize that ARM1176JZ[F]-S support TrustZoneArtyom Skrobov2015-10-292-1/+3
| | | | | | | | | | | | | | Summary: ARMv6KZ cores were set up incorrectly in ARM.td; also, the SMI mnemonic (the old name for SMC, as defined in ARMv6KZ) wasn't supported. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14154 llvm-svn: 251627
* [ARM] Allow SP in rGPR, starting from ARMv8Artyom Skrobov2015-10-284-48/+74
| | | | | | | | | | | | | | | | | Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
* Actually switch the arch when we see .arch. PR21695Roman Divacky2015-10-021-0/+12
| | | | llvm-svn: 249165
* ARM: diagnose invalid local fixups on Thumb1Tim Northover2015-10-027-2/+55
| | | | | | | | | We previously stopped producing Thumb2 relaxations when they weren't supported, but only diagnosed the case where an actual relocation was produced. We should also tell people if local symbols aren't going to work rather than silently overflowing. llvm-svn: 249164
* [ARM] Support for ARMv6-Z / ARMv6-ZK missingArtyom Skrobov2015-09-301-4/+9
| | | | | | | | | | | | | | | As Richard Barton observed at http://reviews.llvm.org/D12937#inline-107121 TargetParser in LLVM has insufficient support for ARMv6Z and ARMv6ZK. In particular, there were no tests for TrustZone being supported in these architectures. The patch clears a FIXME: left by Saleem Abdulrasool in r201471, and fixes his test case which hadn't really been testing what it was claiming to test. Differential Revision: http://reviews.llvm.org/D13236 llvm-svn: 248921
* DI: Require subprogram definitions to be distinctDuncan P. N. Exon Smith2015-08-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | As a follow-up to r246098, require `DISubprogram` definitions (`isDefinition: true`) to be 'distinct'. Specifically, add an assembler check, a verifier check, and bitcode upgrading logic to combat testcase bitrot after the `DIBuilder` change. While working on the testcases, I realized that test/Linker/subprogram-linkonce-weak-odr.ll isn't relevant anymore. Its purpose was to check for a corner case in PR22792 where two subprogram definitions match exactly and share the same metadata node. The new verifier check, requiring that subprogram definitions are 'distinct', precludes that possibility. I updated almost all the IR with the following script: git grep -l -E -e '= !DISubprogram\(.* isDefinition: true' | grep -v test/Bitcode | xargs sed -i '' -e 's/= \(!DISubprogram(.*, isDefinition: true\)/= distinct \1/' Likely some variant of would work for out-of-tree testcases. llvm-svn: 246327
* Fix a bunch of trivial cases of 'CHECK[^:]*$' in the tests. NFCIJonathan Roelofs2015-08-101-1/+1
| | | | | | | I looked into adding a warning / error for this to FileCheck, but there doesn't seem to be a good way to avoid it triggering on the instances of it in RUN lines. llvm-svn: 244481
* If the "CodeView" module flag is set, emit codeview instead of DWARFReid Kleckner2015-08-051-1/+2
| | | | | | | | | | | | | | Summary: Emit both DWARF and CodeView if "CodeView" and "Dwarf Version" module flags are set. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11756 llvm-svn: 244158
* DI: Disallow uniquable DICompileUnitsDuncan P. N. Exon Smith2015-08-031-1/+1
| | | | | | | | | | | | | | | | | | Since r241097, `DIBuilder` has only created distinct `DICompileUnit`s. The backend is liable to start relying on that (if it hasn't already), so make uniquable `DICompileUnit`s illegal and automatically upgrade old bitcode. This is a nice cleanup, since we can remove an unnecessary `DenseSet` (and the associated uniquing info) from `LLVMContextImpl`. Almost all the testcases were updated with this script: git grep -e '= !DICompileUnit' -l -- test | grep -v test/Bitcode | xargs sed -i '' -e 's,= !DICompileUnit,= distinct !DICompileUnit,' I imagine something similar should work for out-of-tree testcases. llvm-svn: 243885
* [ARM] Handle commutativity when converting to tADDhirr in Thumb2Scott Douglass2015-07-132-0/+3
| | | | | | | | Also, run thumb_rewrite.s tests in Thumb2 now that they pass. Differential Revision: http://reviews.llvm.org/D11132 llvm-svn: 242036
* [ARM] Add Thumb2 ADD with SP narrowing from 3 operand to 2Scott Douglass2015-07-131-1/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D11131 llvm-svn: 242035
* [ARM] Small refactor of tryConvertingToTwoOperandForm (nfc)Scott Douglass2015-07-131-3/+77
| | | | | | | | | Also, add more Thumb2 ADD tests requested during review of http://reviews.llvm.org/D11053. Differential Revision: http://reviews.llvm.org/D11130 llvm-svn: 242034
* [ARM] Thumb1 3 to 2 operand convertion for commutative operationsScott Douglass2015-07-092-0/+19
| | | | | | Differential Revision: http://reviews.llvm.org/D11057 llvm-svn: 241802
* [ARM] Don't be overzealous converting Thumb1 3 to 2 operandsScott Douglass2015-07-091-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D11056 llvm-svn: 241801
* [ARM] Add Thumb2 ADD with PC narrowing from 3 operand to 2Scott Douglass2015-07-091-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D11055 llvm-svn: 241800
* [ARM] Refactor converting Thumb1 from 3 to 2 operand (nfc)Scott Douglass2015-07-091-0/+19
| | | | | | | | Also adds some test cases. Differential Revision: http://reviews.llvm.org/D11054 llvm-svn: 241799
* [ARM] Add ADD tests for Thumb2 narrowing (nfc)Scott Douglass2015-07-091-1/+67
| | | | | | Differential Revision: http://reviews.llvm.org/D11053 llvm-svn: 241798
* Reworking the test part of r241149Gabor Ballabas2015-07-021-0/+10
| | | | | | | | | The test part of r241149 has been reverted in r241451, due to misplaced test cases. This patch splits those test cases among the appropriate targets. Differential Revision: http://reviews.llvm.org/D10897 llvm-svn: 241283
* [ARM]: Extend -mfpu options for half-precision and vfpv3xdJaved Absar2015-06-291-0/+5
| | | | | | | | | | | | | | | Some of the the permissible ARM -mfpu options, which are supported in GCC, are currently not present in llvm/clang.This patch adds the options: 'neon-fp16', 'vfpv3-fp16', 'vfpv3-d16-fp16', 'vfpv3xd' and 'vfpv3xd-fp16. These are related to half-precision floating-point and single precision. Reviewers: rengolin, ranjeet.singh Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10645 llvm-svn: 240930
* Revert r240302 ("Bring r240130 back.").Daniel Jasper2015-06-231-1/+1
| | | | | | | | | | | | | This causes errors like: ld: error: blah.o: requires dynamic R_X86_64_PC32 reloc against '' which may overflow at runtime; recompile with -fPIC blah.cc:function f(): error: undefined reference to '' blah.o:g(): error: undefined reference to '' I have not yet come up with an appropriate reproduction. llvm-svn: 240394
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