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* [AArch64] Emit HINT instead of PAC insns in Armv8.2-A or belowPablo Barrio2020-01-131-16/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The Pointer Authentication Extension (PAC) was added in Armv8.3-A. Some instructions are implemented in the HINT space to allow compiling code common to CPUs regardless of whether they feature PAC or not, and still benefit from PAC protection in the PAC-enabled CPUs. The 8.3-specific mnemonics were currently enabled in any architecture, and LLVM was emitting them in assembly files when PAC code generation was enabled. This was ok for compilations where both LLVM codegen and the integrated assembler were used. However, the LLVM codegen was not compatible with other assemblers (e.g. GAS). Given the fact that the approach from these assemblers (i.e. to disallow Armv8.3-A mnemonics if compiling for Armv8.2-A or lower) is entirely reasonable, this patch makes LLVM to emit HINT when building for Armv8.2-A and below, instead of PACIASP, AUTIASP and friends. Then, LLVM assembly should be compatible with other assemblers. Reviewers: samparker, chill, LukeCheeseman Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71658
* [NFC] Fix trivial typos in commentsJames Henderson2020-01-061-2/+2
| | | | | | | | Reviewed By: jhenderson Differential Revision: https://reviews.llvm.org/D72143 Patch by Kazuaki Ishizaki.
* Migrate function attribute "no-frame-pointer-elim"="false" to ↵Fangrui Song2019-12-241-1/+1
| | | | "frame-pointer"="none" as cleanups after D56351
* [AArch64][v8.3a] Don't emit LDRA '[xN]!' alias in disassembly.Simon Tatham2019-11-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Summary: In rG643ac6c0420b, the syntax `ldraa x1, [x0]!` was added as an alias for `ldraa x1, [x0, #0]!`. That syntax is less obvious in meaning, and also will not be accepted by assemblers that haven't been updated yet. So it would be better not to emit it as the preferred disassembly for that instruction. This change lowers the EmitPriority of the new alias so that the more explicit syntax `[x0, #0]!` is preferred by the disassembler. The new syntax is still accepted by the assembler. Reviewers: ab, ostannard Reviewed By: ostannard Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70813
* AArch64: support the Apple NEON syntax for v8.2 crypto instructions.Tim Northover2019-11-271-0/+41
| | | | Very simple change, just adding the extra syntax variant.
* [llvm-objdump] Print relocation addends in hexadecimalDavid Bozier2019-11-193-35/+35
| | | | | | | | | | | | | | Summary: Matches GNU objdump. Makes debugging easier for me as I'm working out addresses from symbol+addend, so it would be good to be calculating in a single format. Reviewers: MaskRay, grimar, jhenderson, bd1976llvm Reviewed By: jhenderson Subscribers: sdardis, jrtc27, atanasyan, rupprecht, seiya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69997
* [AArch64][v8.3a] Add LDRA '[xN]!' alias.Ahmed Bougacha2019-11-131-0/+8
| | | | | | The instruction definition has been retroactively expanded to allow for an alias for '[xN, 0]!' as '[xN]!'. That wouldn't make sense on LDR, but does for LDRA.
* [AArch64] Adding support for PMMIR_EL1 registerVictor Campos2019-10-181-0/+19
| | | | | | | | | | | | | | | | | | Summary: The PMMIR_EL1 register is present in Armv8.4 with PMU extension. This patch adds support for it. Reviewers: t.p.northover, dnsampaio Reviewed By: dnsampaio Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68940 llvm-svn: 375228
* [AArch64,Assembler] Compiler support for ID_MMFR5_EL1Mark Murray2019-10-162-0/+6
| | | | | | | | | | | | Summary: Add read-only system register ID_MMFR5_EL1 and unit tests. Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69039 llvm-svn: 375010
* [AArch64InstPrinter] prefer bfi to bfc for < armv8.2-aNick Desaulniers2019-10-032-6/+17
| | | | | | | | | | | | | | | | | | | Summary: Fixes pr/42576. Link: https://github.com/ClangBuiltLinux/linux/issues/697 Reviewers: t.p.northover Reviewed By: t.p.northover Subscribers: kristof.beyls, hiraditya, llvm-commits, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D68356 llvm-svn: 373655
* AArch64: support arm64_32, an ILP32 slice for watchOS.Tim Northover2019-09-121-0/+15
| | | | | | | | This is the main CodeGen patch to support the arm64_32 watchOS ABI in LLVM. FastISel is mostly disabled for now since it would generate incorrect code for ILP32. llvm-svn: 371722
* [AArch64] Update MTE system register encodingsLuke Cheeseman2019-08-211-10/+10
| | | | | | | | | | The encodings for the system registers TFSRE0_EL1, TFSR_EL1 TFSR_EL2, TFSR_EL3 and TFSR_EL12 have been changed so that they consistently have CRn=5 and CRm=6 as per https://developer.arm.com/docs/ddi0487/latest. Differential Revision: https://reviews.llvm.org/D65442 llvm-svn: 369505
* [MC] Delete unnecessary diagnostic: "No relocation available to represent ↵Fangrui Song2019-08-192-3/+3
| | | | | | | | | | | | | | | | | | | | this relative expression" Replace - error: No relocation available to represent this relative expression with + error: symbol 'undef' can not be undefined in a subtraction expression or + error: Cannot represent a difference across sections Keep !IsPcRel as an assertion after the two diagnostic checks are done. llvm-svn: 369239
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-312-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | Re-commit r366322 after some fixes TME is a future architecture technology, documented in https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools https://developer.arm.com/docs/ddi0601/a More about the future architectures: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and TCANCEL and the target feature/arch extension "tme". It also implements TME builtin functions, defined in ACLE Q2 2019 (https://developer.arm.com/docs/101028/latest) Differential Revision: https://reviews.llvm.org/D64416 Patch by Javed Absar and Momchil Velikov llvm-svn: 367428
* [AArch64][SVE2] Rename bitperm feature to sve2-bitpermCullen Rhodes2019-07-2612-39/+39
| | | | | | | | | | | | | | | | Summary: The bitperm feature flag is now prefixed with SVE2, as it is for all other SVE2 extensions Patch by Maciej Gabka. Reviewers: sdesmalen, rovka, chill, SjoerdMeijer, rengolin Reviewed By: SjoerdMeijer, rengolin Differential Revision: https://reviews.llvm.org/D65327 llvm-svn: 367124
* [AArch64] Define ETE and TRBE system registersMomchil Velikov2019-07-263-0/+77
| | | | | | | | | | | | | | | | | | | | Embedded Trace Extension and Trace Buffer Extension are optional future architecture extensions. (cf. https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools) Their system registers are documented here: https://developer.arm.com/docs/ddi0601/a ETE shares register names with ETM. One exception is the ETE TRCEXTINSELR0 register, which has the same encoding as the ETM TRCEXTINSELR register (but different semantics). This patch treats them as aliases: the assembler will accept both names, emitting identical encoding, and the disassembler will keep disassembling to TRCEXRINSELR. Differential Revision: https://reviews.llvm.org/D63707 llvm-svn: 367093
* [AArch64][SVE] Allow explicit size specifier for predicate operandMomchil Velikov2019-07-256-29/+137
| | | | | | | | | | | | | ... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue supporting the exsting behaviour of not requiring an explicit size specifier. The preferred disasembly is *with* the specifier. This is implemented by redefining intruction forms to require vector predicates with explicit size and adding aliases, which allow a predicate with no size. Differential Revision: https://reviews.llvm.org/D65145 llvm-svn: 367019
* [ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1Pablo Barrio2019-07-254-3/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add support for Cortex-A65, Cortex-A65AE, Neoverse E1 and Neoverse N1. Neoverse E1 and Cortex-A65(&AE) only implement the AArch64 state of the Arm architecture. Neoverse N1 implements both AArch32 and AArch64. Cortex-A65: https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65 Cortex-A65AE: https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65ae Neoverse E1: https://developer.arm.com/ip-products/processors/neoverse/neoverse-e1 Neoverse N1: https://developer.arm.com/ip-products/processors/neoverse/neoverse-n1 Patch by Diogo Sampaio and Pablo Barrio Reviewers: samparker, LukeCheeseman, sbaranga, ostannard Reviewed By: ostannard Subscribers: ostannard, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64406 llvm-svn: 367007
* MC: AArch64: Add support for prel_g* relocation specifiers.Peter Collingbourne2019-07-181-5/+33
| | | | | | Differential Revision: https://reviews.llvm.org/D64683 llvm-svn: 366462
* AArch64: Unify relocation restrictions between MOVK/MOVN/MOVZ.Peter Collingbourne2019-07-181-54/+0
| | | | | | | | | | | | | | | | | | | | | | | There doesn't seem to be a practical reason for these instructions to have different restrictions on the types of relocations that they may be used with, notwithstanding the language in the ELF AArch64 spec that implies that specific relocations are meant to be used with specific instructions. For example, we currently forbid the first instruction in the following sequence, despite it currently being used by clang to generate a global reference under -mcmodel=large: movz x0, #:abs_g0_nc:foo movk x0, #:abs_g1_nc:foo movk x0, #:abs_g2_nc:foo movk x0, #:abs_g3:foo Therefore, allow MOVK/MOVN/MOVZ to accept the union of the set of relocations that they currently accept individually. Differential Revision: https://reviews.llvm.org/D64466 llvm-svn: 366461
* Revert [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-172-71/+0
| | | | | | This reverts r366322 (git commit 4b8da3a503e434ddbc08ecf66582475765f449bc) llvm-svn: 366355
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-172-0/+71
| | | | | | | | | | | | | | | | | | | | | | | TME is a future architecture technology, documented in https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools https://developer.arm.com/docs/ddi0601/a More about the future architectures: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and TCANCEL and the target feature/arch extension "tme". It also implements TME builtin functions, defined in ACLE Q2 2019 (https://developer.arm.com/docs/101028/latest) Patch by Javed Absar and Momchil Velikov Differential Revision: https://reviews.llvm.org/D64416 llvm-svn: 366322
* MC: AArch64: Add support for pg_hi21_nc relocation specifier.Peter Collingbourne2019-07-101-0/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D64455 llvm-svn: 365661
* [AArch64][AsmParser] error on unexpected SVE predicate type suffixCullen Rhodes2019-06-0756-33/+678
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch fixes a bug in the assembler that permitted a type suffix on predicate registers when not expected. For instance, the following was previously valid: faddv h0, p0.q, z1.h This bug was present in all SVE instructions containing predicates with no type suffix and no predication form qualifier, i.e. /z or /m. The latter instructions are already caught with an appropiate error message by the assembler, e.g.: .text <stdin>:1:13: error: not expecting size suffix cmpne p1.s, p0.b/z, z2.s, 0 ^ A similar issue for SVE vector registers was fixed in: https://reviews.llvm.org/D59636 Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62942 llvm-svn: 362780
* [AArch64][AsmParser] Provide better diagnostics for SVE predicatesCullen Rhodes2019-06-07249-340/+340
| | | | | | | | | | Patch by Sander de Smalen (sdesmalen) Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62941 llvm-svn: 362779
* [AArch64][SVE2] Add CPU and arch directive testsCullen Rhodes2019-06-036-0/+156
| | | | | | | | | | | | Summary: This patch adds tests for directives .arch, .arch_extension and .cpu for all features defined in Arm SVE2 architecture extension. Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62602 llvm-svn: 362378
* [AArch64][SVE2] Asm: support WHILE instructionsCullen Rhodes2019-05-3112-0/+502
| | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: * WHILEGE, WHILEGT, WHILEHS, WHILEHI, WHILEWR, WHILERW The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62601 llvm-svn: 362215
* [AArch64][SVE2] Asm: support TBL/TBX instructionsCullen Rhodes2019-05-314-0/+137
| | | | | | | | | | | | | | | | | Summary: A three sources variant of the TBL instruction is added to the existing SVE instruction in SVE2. This is implemented with minor changes to the existing TableGen class. TBX is a new instruction with its own definition. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62600 llvm-svn: 362214
* [AArch64][SVE2] Asm: support SVE2 store instructionsCullen Rhodes2019-05-319-2/+614
| | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: * STNT1B, STNT1H, STNT1S, STNT1D The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62599 llvm-svn: 362213
* [AArch64][SVE2] Asm: support SVE2 vector splice (constructive)Cullen Rhodes2019-05-302-0/+115
| | | | | | | | | | | | Summary: The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62530 llvm-svn: 362073
* [AArch64][SVE2] Asm: support SVE2 load instructionsCullen Rhodes2019-05-3015-2/+1127
| | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: * LDNT1SB, LDNT1B, LDNT1SH, LDNT1H, LDNT1SW, LDNT1W, LDNT1D The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62528 llvm-svn: 362072
* [AArch64][SVE2] Asm: support FCVTX/FLOGB instructionsCullen Rhodes2019-05-304-0/+175
| | | | | | | | | | | | | | | | | Summary: Patch completes SVE2 support for: SVE Floating Point Unary Operations - Predicated Group The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62526 llvm-svn: 362071
* [AArch64][SVE2] Asm: add ext (immediate offset, constructive) instructionCullen Rhodes2019-05-302-0/+104
| | | | | | | | | | | | Summary: The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62518 llvm-svn: 362070
* [AArch64][SVE2] Asm: support SVE Bitwise Logical - Unpredicated GroupCullen Rhodes2019-05-2914-0/+590
| | | | | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: * EOR3, BSL, BCAX, BSL1N, BSL2N, NBSL, XAR Aliases for types .B/.H/.S for EOR3 and BCAX have been added, the preferred disassembly is .D. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62387 llvm-svn: 361936
* [AArch64][SVE2] Asm: support Floating Point Widening Multiply-AddCullen Rhodes2019-05-299-0/+510
| | | | | | | | | | | | | | | Summary: Patch adds support for the indexed and unpredicated vectors forms of the FMLALB, FMLALT, FMLSLB and FMLSLT instructions. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62386 llvm-svn: 361935
* [AArch64][SVE2] Asm: support SVE2 Floating Point Pairwise GroupCullen Rhodes2019-05-2910-0/+515
| | | | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: SVE2 floating-point pairwise operations: * FADDP, FMAXNMP, FMINNMP, FMAXP, FMINP The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62383 llvm-svn: 361933
* [AArch64][SVE2] Asm: support SVE2 Floating Point Convert GroupCullen Rhodes2019-05-286-0/+275
| | | | | | | | | | | | | | | | | Summary: Patch adds support for the following intructions: SVE2 floating-point convert precision: * FCVTXNT, FCVTNT, FCVTLT The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62382 llvm-svn: 361801
* [AArch64][SVE2] Asm: support SVE2 Crypto Extensions GroupCullen Rhodes2019-05-2814-0/+414
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: SVE2 crypto constructive binary operations: * SM4EKEY, RAX1 SVE2 crypto destructive binary operations: * AESE, AESD, SM4E SVE2 crypto unary operations: * AESMC, AESIMC AESE, AESD, AESMC and AESIMC are enabled with +sve2-aes. SM4E and SM4EKEY are enabled with +sve2-sm4. RAX1 is enabled with +sve2-sha3. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62307 llvm-svn: 361797
* [AArch64][SVE2] Asm: support SVE2 Histogram Computation GroupsCullen Rhodes2019-05-284-0/+121
| | | | | | | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: SVE2 histogram generation (segment): * HISTSEG SVE2 histogram generation (vector): * HISTCNT The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62306 llvm-svn: 361796
* [AArch64][SVE2] Asm: support SVE2 Misc GroupCullen Rhodes2019-05-2824-0/+971
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: SVE2 bitwise exclusive-or interleaved: * EORBT, EORTB SVE2 bitwise permute: * BEXT, BDEP, BGRP SVE2 bitwise shift left long: * SSHLLB, SSHLLT, USHLLB, USHLLT SVE2 integer add/subtract interleaved long: * SADDLBT, SSUBLBT, SSUBLTB BDEP, BEXT and BGRP are enabled with SVE2 feature +bitperm, all other instructions in this group are enabled with +sve2. Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62304 llvm-svn: 361795
* [AArch64][SVE2] Asm: support SVE2 String Processing GroupCullen Rhodes2019-05-244-0/+186
| | | | | | | | | | | | | | Summary: Patch adds support for the SVE2 character match instructions MATCH and NMATCH. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62206 llvm-svn: 361627
* [AArch64][SVE2] Asm: support SVE2 Narrowing GroupCullen Rhodes2019-05-2460-0/+2682
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: SVE2 bitwise shift right narrow: * SQSHRUNB, SQSHRUNT, SQRSHRUNB, SQRSHRUNT, SHRNB, SHRNT, RSHRNB, RSHRNT, SQSHRNB, SQSHRNT, SQRSHRNB, SQRSHRNT, UQSHRNB, UQSHRNT, UQRSHRNB, UQRSHRNT SVE2 integer add/subtract narrow high part: * ADDHNB, ADDHNT, RADDHNB, RADDHNT, SUBHNB, SUBHNT, RSUBHNB, RSUBHNT SVE2 saturating extract narrow: * SQXTNB, SQXTNT, UQXTNB, UQXTNT, SQXTUNB, SQXTUNT The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62205 llvm-svn: 361624
* [AArch64][SVE2] Asm: support SVE2 Accumulate GroupCullen Rhodes2019-05-2436-0/+1667
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: SVE2 bitwise shift and insert: * SRI, SLI SVE2 bitwise shift right and accumulate: * SSRA, USRA, SRSRA, URSRA SVE2 complex integer add: * CADD, SQCADD SVE2 integer absolute difference and accumulate: * SABA, UABA SVE2 integer absolute difference and accumulate long: * SABALB, SABALT, UABALB, UABALT SVE2 integer add/subtract long with carry: * ADCLB, ADCLT, SBCLB, SBCLT The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62204 llvm-svn: 361622
* [AArch64][SVE2] Asm: add PMULLB/PMULLT instructionsCullen Rhodes2019-05-248-0/+212
| | | | | | | | | | | | | | | | | Summary: This patch adds support for the polynomial multiplication instructions PMULLB/PMULLT. The 64-bit source and 128-bit destination element variants are enabled with crypto extensions (+sve2-aes), similar to the NEON PMULL2 instruction. All other variants are enabled with +sve2. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62145 llvm-svn: 361619
* [AArch64][SVE2] Asm: add integer add/sub long/wide instructionsCullen Rhodes2019-05-2440-0/+1340
| | | | | | | | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: SVE2 integer add/subtract long: * SADDLB, SADDLT, UADDLB, UADDLT, SSUBLB, SSUBLT, USUBLB, USUBLT, SABDLB, SABDLT, UABDLB, UABDLT SVE2 integer add/subtract wide: * SADDWB, SADDWT, UADDWB, UADDWT, SSUBWB, SSUBWT, USUBWB, USUBWT The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62142 llvm-svn: 361615
* [AArch64][SVE2] Asm: add various bitwise shift instructionsCullen Rhodes2019-05-2430-0/+1903
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds support for the SVE2 saturating/rounding bitwise shift left (predicated) group of instructions: * SRSHL, URSHL, SRSHLR, URSHLR, SQSHL, UQSHL, SQRSHL, UQRSHL, SQSHLR, UQSHLR, SQRSHLR, UQRSHLR Immediate forms of the SQSHL and UQSHL instructions are also added to the existing SVE bitwise shift by immediate (predicated) group, as well as three new instructions SRSHR/URSHR/SQSHLU. The new instructions in this group are encoded similarly and are implemented using the same TableGen class with a minimal change (1 bit in encoding). The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62140 llvm-svn: 361612
* [AArch64][SVE2] Asm: add saturating add/sub instructionsCullen Rhodes2019-05-2416-0/+768
| | | | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: * SQADD, UQADD, SUQADD, USQADD * SQSUB, UQSUB, SQSUBR, UQSUBR The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62130 llvm-svn: 361611
* [AArch64][SVE2] Asm: add integer unary instructions (predicated)Cullen Rhodes2019-05-218-0/+316
| | | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: * URECPE, URSQRTE, SQABS, SQNEG The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62129 llvm-svn: 361230
* [AArch64][SVE2] Asm: add integer pairwise arithmetic instructionsCullen Rhodes2019-05-2110-0/+480
| | | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: ADDP, SMAXP, UMAXP, SMINP, UMINP The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62128 llvm-svn: 361229
* [AArch64][SVE2] Asm: add SADALP and UADALP instructionsCullen Rhodes2019-05-204-0/+190
| | | | | | | | | | | | | | | Summary: This patch adds support for the integer pairwise add and accumulate long instructions SADALP/UADALP. These instructions are predicated. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62001 llvm-svn: 361154
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