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* MIRParser: Use shorter cfi identifiersMatthias Braun2016-07-2617-63/+63
| | | | | | | | | | | | | | | | In an instruction like: CFI_INSTRUCTION .cfi_def_cfa ... we can drop the '.cfi_' prefix since that should be obvious by the context: CFI_INSTRUCTION def_cfa ... While being a terser and cleaner syntax this also prepares to dropping support for identifiers starting with a dot character so we can use it for expressions. Differential Revision: http://reviews.llvm.org/D22388 llvm-svn: 276785
* GlobalISel: add correct operand type to G_FRAME_INDEX instrs.Tim Northover2016-07-261-3/+3
| | | | | | Frame indices should use "addFrameIndex", not "addImm". llvm-svn: 276775
* [Hexagon] Add support for proper handling of H and L constraintsKrzysztof Parzyszek2016-07-261-0/+16
| | | | | | | | | H -> High part of reg pair. L -> Low part of reg pair. Patch by Sundeep Kushwaha. llvm-svn: 276773
* GlobalISel: omit braces on MachineInstr types when there's only one.Tim Northover2016-07-265-52/+52
| | | | | | Tidies up the representation a bit in the common case. llvm-svn: 276772
* AMDGPU: Add missing tests for xnack option for HSAMatt Arsenault2016-07-261-5/+21
| | | | llvm-svn: 276765
* AMDGPU: Add fp legacy instruction intrinsicsMatt Arsenault2016-07-262-0/+96
| | | | | | | This could use some additional optimization work to use mad/mac legacy. llvm-svn: 276764
* [X86][SSE] Added extra memory folding tests for cvtsd2ss intrinsicSimon Pilgrim2016-07-261-0/+36
| | | | | | SSE only fold partial reg update instructions when optsize is enabled llvm-svn: 276743
* [X86][SSE] Fixed issue with memory folding of (v)cvtsd2ss intrinsicsSimon Pilgrim2016-07-262-0/+56
| | | | | | | | Fixed typo in the intrinsic definitions of (v)cvtsd2ss with memory folding. This was only unearthed when rL276102 started using the intrinsic again..... llvm-svn: 276740
* [mips] MIPS64R6 compact branch supportSimon Dardis2016-07-263-6/+289
| | | | | | | | | | | | | MIPS64R6 compact branch support. As the MIPS LLVM backend uses distinct MachineInstrs for certain 32 and 64 bit instructions (e.g. BEQ & BEQ64) that map to the same instruction, extend compact branch support for the corresponding 64bit branches. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D20164 llvm-svn: 276739
* [ARM] Saturation instructions are DSP-onlyRenato Golin2016-07-253-10/+38
| | | | | | | | | | | The saturation instructions appeared in v6T2, with DSP extensions, but they were being accepted / generated on any, with the new introduction of the saturation detection in the back-end. This commit restricts the usage to DSP-enable only cores. Fixes PR28607. llvm-svn: 276701
* [X86] Regenerate v2i256 shift legalization testsSimon Pilgrim2016-07-251-26/+116
| | | | llvm-svn: 276692
* [X86] Regenerate i64 shift legalization testsSimon Pilgrim2016-07-251-38/+160
| | | | llvm-svn: 276691
* GlobalISel: add generic casts to IRTranslatorTim Northover2016-07-251-9/+51
| | | | | | | | | This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the IRTranslator. The first two are direct translations (with 2 MachineInstr types each). Since LLT discards information, a bitcast might become trivial and we emit a COPY in those cases instead. llvm-svn: 276690
* GlobalISel[AArch64]: support pointer types in argument lowering.Tim Northover2016-07-251-0/+52
| | | | | | | | They're basically i64 for AArch64, but we'll leave them intact for stranger targets. Also add some tests for the (very few) other cases we can handle right now. llvm-svn: 276689
* AMDGPU: Remove read_workdim intrinsicJan Vesely2016-07-254-115/+0
| | | | | | Differential revision: https://reviews.llvm.org/D22732 llvm-svn: 276682
* AMDGPU: Fix missing verify-machineinstrs in control flow testMatt Arsenault2016-07-251-1/+1
| | | | llvm-svn: 276679
* [X86][SSE] Added 2048-bit vector comparison testsSimon Pilgrim2016-07-251-0/+1757
| | | | | | Upper limit of what can be held in a <32 x i8> result llvm-svn: 276666
* AVX-512: Fixed [US]INT_TO_FP selection for i1 vectors.Elena Demikhovsky2016-07-251-0/+347
| | | | | | | | It failed with assertion before this patch. Differential Revision: https://reviews.llvm.org/D22735 llvm-svn: 276648
* [Hexagon] Add target feature to generate long callsKrzysztof Parzyszek2016-07-251-0/+73
| | | | llvm-svn: 276638
* [ARM] Improve longMAC codegen testSam Parker2016-07-251-34/+85
| | | | | | | | Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
* [mips] Optimize materialization of i64 constantsSimon Dardis2016-07-259-80/+85
| | | | | | | | | | | | | | | | | Avoid MipsAnalyzeImmediate usage if the constant fits in an 32-bit integer. This allows us to generate the same instructions for the materialization of the same constants regardless the width of their type. Patch by: Vasileios Kalintiris Contributions by: Simon Dardis Reviewers: Daniel Sanders Differential Review: https://reviews.llvm.org/D21689 llvm-svn: 276628
* [ARM] Enable ISel of SMMLS for ARM and Thumb2Sam Parker2016-07-251-2/+34
| | | | | | | | Use ISelDAGToDAG to recognise the SMMLS instruction pattern. Differential Revision: https://reviews.llvm.org/D22562 llvm-svn: 276624
* [AVX512] Add load folding support for the unmasked forms of the FMA ↵Craig Topper2016-07-252-8/+4
| | | | | | instructions. llvm-svn: 276615
* [AVX512] Add some additional patterns so that we can fold broadcast loads in ↵Craig Topper2016-07-251-4/+2
| | | | | | the first argument of an FMADD/FMSUB/FNMADD/FNMSUB/FMADDSUB/FMSUBADD node. Also add patterns to support all combinations of the broadcast input and the preserved input for masked versions. llvm-svn: 276614
* [AVX512] Cleanup FMA operand order in patterns to match the VEX versions and ↵Craig Topper2016-07-253-243/+266
| | | | | | to really be 213, 231, and 132. llvm-svn: 276613
* [X86][SSE] Added PR27854 tests Simon Pilgrim2016-07-241-0/+48
| | | | llvm-svn: 276571
* [X86] Add shift double tests for PR14593Simon Pilgrim2016-07-241-0/+74
| | | | llvm-svn: 276570
* [X86] Add 'FeatureSlowSHLD' to cpu 'bdver4'Simon Pilgrim2016-07-241-0/+2
| | | | | | As with all AMD CPUs, excavator has poor SHLD/SHRD performance. Also added bdver3 to the test as it was missing. llvm-svn: 276569
* [X86] Add SHRD shift combine testsSimon Pilgrim2016-07-241-0/+36
| | | | llvm-svn: 276568
* [X86] Regenerate shift by parts testsSimon Pilgrim2016-07-241-7/+77
| | | | llvm-svn: 276567
* [X86][SSE] Regenerate shifts testsSimon Pilgrim2016-07-241-72/+245
| | | | llvm-svn: 276566
* [X86][SSE] Regenerate SSE copysign testsSimon Pilgrim2016-07-241-82/+102
| | | | llvm-svn: 276565
* [X86][AVX512VL] Added AVX512VL half2float vector conversions tests to ↵Simon Pilgrim2016-07-241-1756/+4175
| | | | | | demonstrate PR23941 llvm-svn: 276563
* [X86] Make the FMA3 instruction names consistent between VEX and EVEX ↵Craig Topper2016-07-241-4/+4
| | | | | | | | encoded versions. This places the 132/213/231 form number in front of the SS/SD/PS/PD. Move the Y for 256-bit versions to be after the PS/PD. Change the AVX512 scalar forms to include a Z in the their name. This new format should be consistent with the general naming of instructions. llvm-svn: 276559
* [X86][SSE] Added float widened broadcast testsSimon Pilgrim2016-07-231-0/+83
| | | | llvm-svn: 276535
* [X86][SSE] Added more widened broadcast testsSimon Pilgrim2016-07-231-5/+368
| | | | | | Added more vXi16 and vXi8 tests llvm-svn: 276534
* [X86][SSE] Added tests where we should be trying to widen a load+splat into ↵Simon Pilgrim2016-07-231-0/+149
| | | | | | a broadcast llvm-svn: 276527
* [X86][SSE] Regenerated uitofp <2 x i32> -> <2 x float> conversion testsSimon Pilgrim2016-07-231-16/+51
| | | | | | Demonstrate difference in codegen discussed on PR14760 llvm-svn: 276526
* [AVX512] Implement commuting support for EVEX encoded FMA3 instructions.Craig Topper2016-07-233-86/+42
| | | | llvm-svn: 276521
* Revert "[AMDGPU] Emit read-only data to .rodata for hsa"Tom Stellard2016-07-222-2/+2
| | | | | | | | | | | | This reverts commit r276298. Data stored in .rodata can have a negative offset from .text, but we don't support negative values in relocations yet. This caused a regression in one of the amp conformance tests: 5_Data_Cont/5_2_a_v/5_2_3_m/Assignment/Test.02.01 llvm-svn: 276498
* GlobalISel: allow multiple types on MachineInstrs.Tim Northover2016-07-225-52/+52
| | | | llvm-svn: 276481
* GlobalISel: implement legalization pass, with just one transformation.Tim Northover2016-07-221-0/+34
| | | | | | | | | This adds the actual MachineLegalizeHelper to do the work and a trivial pass wrapper that legalizes all instructions in a MachineFunction. Currently the only transformation supported is splitting up a vector G_ADD into one acting on smaller vectors. llvm-svn: 276461
* Invariant start/end intrinsics overloaded for address spaceAnna Thomas2016-07-221-4/+4
| | | | | | | | | | | | | | | | | | | | | | Summary: The llvm.invariant.start and llvm.invariant.end intrinsics currently support specifying invariant memory objects only in the default address space. With this change, these intrinsics are overloaded for any adddress space for memory objects and we can use these llvm invariant intrinsics in non-default address spaces. Example: llvm.invariant.start.p1i8(i64 4, i8 addrspace(1)* %ptr) This overloaded intrinsic is needed for representing final or invariant memory in managed languages. Reviewers: apilipenko, reames Subscribers: llvm-commits llvm-svn: 276447
* AMDGPU: Remove redundant testMatt Arsenault2016-07-222-115/+1
| | | | llvm-svn: 276439
* AMDGPU: Fix groupstaticsize for large LDSMatt Arsenault2016-07-221-2/+15
| | | | | | | | | The size can exceed s_movk_i32's limit, and we don't want to use it this early since it inhibits optimizations. This should probably be merged to the release branch. llvm-svn: 276438
* AMDGPU: Add HSA dispatch id intrinsicMatt Arsenault2016-07-221-0/+19
| | | | llvm-svn: 276437
* AMDGPU: Fix i1 fp_to_intMatt Arsenault2016-07-224-7/+97
| | | | | | | R600's i1 fp_to_uint selected but was incorrect according to what instcombine constant folds to. llvm-svn: 276435
* GlobalISel: implement alloca instructionTim Northover2016-07-222-1/+17
| | | | llvm-svn: 276433
* [SelectionDAG] Optimization of BITREVERSE legalization for power-of-2 ↵Simon Pilgrim2016-07-223-2502/+1005
| | | | | | | | | | | | | | integer scalar/vector types An extension of D19978, this patch replaces the default BITREVERSE evaluation of individual bit masks+shifts with block mask+shifts when we have integer elements of power-of-2 bits in size. After calling BSWAP to reverse the order of the constituent bytes (which typically follows a similar approach), every neighbouring 4-bits, 2-bits and finally 1-bit pairs are masked off and swapped over with shifts. In doing so we can significantly reduce the number of operations required. Differential Revision: https://reviews.llvm.org/D21578 llvm-svn: 276432
* [Hexagon] Use loop data prefetch on HexagonKrzysztof Parzyszek2016-07-221-0/+27
| | | | llvm-svn: 276422
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