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* [X86] Don't report gather is legal on Skylake CPUs when AVX2/AVX512 is ↵Craig Topper2017-11-251-0/+480
| | | | | | | | | | | | | | | | | | | disabled. Allow gather on SKX/CNL/ICL when AVX512 is disabled by using AVX2 instructions. Summary: This adds a new fast gather feature bit to cover all CPUs that support fast gather that we can use independent of whether the AVX512 feature is enabled. I'm only using this new bit to qualify AVX2 codegen. AVX512 is still implicitly assuming fast gather to keep tests working and to match the scatter behavior. Test command lines have been added for these two cases. Reviewers: magabari, delena, RKSimon, zvi Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40282 llvm-svn: 318983
* Add BTVER2 sched support for SHLD/SHRD.Andrew V. Tischenko2017-11-251-24/+24
| | | | | | Differential Revision: https://reviews.llvm.org/D40124 llvm-svn: 318977
* [X86] Support folding to andnps with SSE1 only.Craig Topper2017-11-251-4/+2
| | | | | | With SSE1 only, we emit FAND and FXOR nodes for v4f32. llvm-svn: 318968
* [X86] Add some early DAG combines to turn v4i32 AND/OR/XOR into ↵Craig Topper2017-11-253-268/+70
| | | | | | | | | | FAND/FOR/FXOR whe only SSE1 is available. v4i32 isn't a legal type with sse1 only and would end up getting scalarized otherwise. This isn't completely ideal as it doesn't handle cases like v8i32 that would get split to v4i32. But it at least helps with code written using the clang intrinsic header. llvm-svn: 318967
* [X86] Prevent using X * rsqrt(X) to approximate sqrt when only sse1 is enabled.Craig Topper2017-11-241-112/+6
| | | | | | | | This optimization can occur after type legalization and emit a vselect with v4i32 type. But that type is not legal with sse1. This ultimately gets scalarized by the second type legalization that runs after vector op legalization, but that's really intended to handle the scalar types that might be introduced by legalizing vector ops. For now just stop this from happening by disabling the optimization with sse1. llvm-svn: 318965
* [AVR] Use the short form of 'clr <reg>'Dylan McKay2017-11-243-10/+10
| | | | | | | r318895 made it so that the simpler instruction aliases are printed rather than their expanded form. llvm-svn: 318954
* [mips] Set microMIPS ASE flagAleksandar Beserminji2017-11-241-0/+11
| | | | | | | | | | This patch fixes an issue where microMIPS ASE flag is not set when a function has micromips attribute or when .set micromips directive is used. Differential Revision: https://reviews.llvm.org/D40316 llvm-svn: 318948
* [X86] Don't invert NewCC variable while processing the jcc/setcc/cmovcc ↵Craig Topper2017-11-231-0/+22
| | | | | | | | | | instructions in optimizeCompareInstr. The NewCC variable is calculated outside of the loop that processes jcc/setcc/cmovcc instructions. If we invert it during the loop it can cause an incorrect value to be used by a later iteration. Instead only read it during the loop and use a new variable to store the possibly inverted value. Fixes PR35399. llvm-svn: 318934
* [X86] Teach isel that X86ISD::CMPM_RND zeros the upper bits of the mask ↵Craig Topper2017-11-231-2/+114
| | | | | | register. llvm-svn: 318933
* [X86][SSE] Use (V)PHMINPOSUW for vXi16 SMAX/SMIN/UMAX/UMIN horizontal ↵Simon Pilgrim2017-11-234-572/+522
| | | | | | | | | | | | | | reductions (PR32841) (V)PHMINPOSUW determines the UMIN element in an v8i16 input, with suitable bit flipping it can also be used for SMAX/SMIN/UMAX cases as well. This patch matches vXi16 SMAX/SMIN/UMAX/UMIN horizontal reductions and reduces the input down to a v8i16 vector before calling (V)PHMINPOSUW. A later patch will use this for v16i8 reductions as well (PR32841). Differential Revision: https://reviews.llvm.org/D39729 llvm-svn: 318917
* [ARM GlobalISel] Support G_FDIV for s32 and s64Diana Picus2017-11-233-0/+208
| | | | | | | | | | | | TableGen already generates code for selecting a G_FDIV, so we only need to add a test. For the legalizer and reg bank select, we do the same thing as for the other floating point binary operations: either mark as legal if we have a FP unit or lower to a libcall, and map to the floating point registers. llvm-svn: 318915
* [ARM GlobalISel] Support G_FMUL for s32 and s64Diana Picus2017-11-233-0/+208
| | | | | | | | | | | TableGen already generates code for selecting a G_FMUL, so we only need to add a test for that part. For the legalizer and reg bank select, we do the same thing as the other floating point binary operators: either mark as legal if we have a FP unit or lower to a libcall, and map to the floating point registers. llvm-svn: 318910
* [mips] Use the delay slot filler to convert branches for microMIPSR6.Simon Dardis2017-11-233-6/+5
| | | | | | | | | | | | | | | | | | The MIPS delay slot filler converts delay slot branches into compact forms for the MIPS ISAs which support them. For branches that compare (in)equality with with zero, it converts them into branches with implict zero register operands. These branches have a slightly greater range than normal two register operands branches. Changing the branches at this point in the pipeline offers the long branch pass the ability to mark better judgements if a long branch sequence is required. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D40314 llvm-svn: 318908
* [x86][icelake]BITALGCoby Tayree2017-11-231-0/+41
| | | | | | | | | | 2/3 vpshufbitqmb encoding 3/3 vpshufbitqmb intrinsics Differential Revision: https://reviews.llvm.org/D40222 llvm-svn: 318904
* [X86] Regenerate the vector-popcnt and vector-tzcnt tests to get BITALG ↵Craig Topper2017-11-226-0/+870
| | | | | | CHECK linse on all functions not just the vXi16/vXi8. llvm-svn: 318885
* [Hexagon] Implement buildVector32 and buildVector64 as utility functionsKrzysztof Parzyszek2017-11-223-2/+12
| | | | | | | | | Change LowerBUILD_VECTOR to use those functions. This commit will tempora- rily affect constant vector generation (it will generate constant-extended values instead of non-extended combines), but the code for the general case should be better. The constant selection part will be fixed later. llvm-svn: 318877
* [Hexagon] Add patterns to select A2_combine_ll and its variantsKrzysztof Parzyszek2017-11-222-1/+44
| | | | llvm-svn: 318876
* [Hexagon] Remove trailing spaces, NFCKrzysztof Parzyszek2017-11-226-6/+6
| | | | llvm-svn: 318875
* [X86] Support v32i16/v64i8 CTLZ using lookup table.Craig Topper2017-11-221-70/+48
| | | | | | Had to tweak the setcc's used by the code to use a vXi1 result type with a sign extend back to vector size. llvm-svn: 318871
* [AMDGPU] Fix SITargetLowering::LowerCall for pointer info of byval argumentYaxun Liu2017-11-221-26/+27
| | | | | | | | | | | SITargetLowering::LowerCall uses dummy pointer info for byval argument, which causes flat load instead of buffer load. This patch fixes that. Differential Revision: https://reviews.llvm.org/D40040 llvm-svn: 318844
* AMDGPU: Consider memory dependencies with moved instructions in ↵Nicolai Haehnle2017-11-221-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SILoadStoreOptimizer Summary: This bug seems to have gone unnoticed because critical cases with LDS instructions are eliminated by the peephole optimizer. However, equivalent situations arise with buffer loads and stores as well, so this fixes regressions since r317751 ("AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4"). Fixes at least: KHR-GL45.shader_storage_buffer_object.basic-operations-case1-cs KHR-GL45.cull_distance.functional piglit tes-input-gl_ClipDistance.shader_test ... and probably more Change-Id: I0e371536288eb8e6afeaa241a185266fd45d129d Reviewers: arsenm, mareko, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D40303 llvm-svn: 318829
* [DAGCombiner] Bugfix in isAlias().Jonas Paulsson2017-11-221-0/+143
| | | | | | | | | | | | | | | | | Since i1 is a legal type, this: NumBytes = Op1->getMemoryVT().getSizeInBits() >> 3; is wrong and should be instead NumBytes = Op0->getMemoryVT().getStoreSize(); There seems to be more places where this should be fixed outside DAGCombiner. Review: Hal Finkel https://bugs.llvm.org/show_bug.cgi?id=35366 llvm-svn: 318824
* [Hexagon] Make sure that RDF does not remove EH_LABELsKrzysztof Parzyszek2017-11-211-0/+17
| | | | | | | Since EH_LABELs (and other labels) no longer have "side-effects", they should be checked for separately. llvm-svn: 318801
* [X86] Allow vpclmulqdq instructions to be commuted during isel to allow load ↵Craig Topper2017-11-211-2/+3
| | | | | | | | folding. The commuting patterns for the AVX version actually still had priority over the new patterns. llvm-svn: 318800
* [AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as *having* side effects.Chad Rosier2017-11-211-60/+0
| | | | | | | | | | | | | | | | | | | This partially reverts r298851. The the underlying issue is that we don't currently model the dependency between mrs (read system register) and msr (write system register) instructions. Something like the below should never be reordered: msr TPIDR_EL0, x0 ;; set thread pointer mrs x8, TPIDR_EL0 ;; read thread pointer but was being reordered after r298851. The functional part of the patch that wasn't reverted needed to remain in place in order to not break r299462. PR35317 llvm-svn: 318788
* [MI scheduler] Fix VADD and VSUB in cortex-a57 modelEugene Leviant2017-11-212-0/+52
| | | | | | | | This patch fixes instregex for interger vector add/sub instructions Differential revision: https://reviews.llvm.org/D40254 llvm-svn: 318749
* [x86][icelake]BITALGCoby Tayree2017-11-216-0/+176
| | | | | | | vpopcnt{b,w} Differential Revision: https://reviews.llvm.org/D40213 llvm-svn: 318748
* [ARM GlobalISel] Add comment for r318398. NFC.Diana Picus2017-11-211-0/+5
| | | | | | | Mention the purpose of the BICri tests added by r318398, as requested in post-commit review. llvm-svn: 318747
* [x86][icelake]VNNICoby Tayree2017-11-212-0/+293
| | | | | | | | | Introducing Vector Neural Network Instructions, consisting of: vpdpbusd{s} vpdpwssd{s} Differential Revision: https://reviews.llvm.org/D40208 llvm-svn: 318746
* [x86][icelake]vbmi2Coby Tayree2017-11-212-0/+984
| | | | | | | | | | | introducing vbmi2, consisting of vpcompress{b,w} vpexpand{b,w} vpsh{l,r}d{w,d,q} vpsh{l,r}dv{w,d,q} Differential Revision: https://reviews.llvm.org/D40206 llvm-svn: 318745
* [x86][icelake]vpclmulqdq introductionCoby Tayree2017-11-215-0/+204
| | | | | | | an icelake promotion of pclmulqdq Differential Revision: https://reviews.llvm.org/D40101 llvm-svn: 318741
* [x86][icelake]VAES introductionCoby Tayree2017-11-213-0/+137
| | | | | | | an icelake promotion of AES Differential Revision: https://reviews.llvm.org/D40078 llvm-svn: 318740
* [RISCV] Use register X0 (ZERO) for constant 0Alex Bradbury2017-11-213-29/+13
| | | | | | | | | | | | The obvious approach of defining a pattern like the one below actually doesn't work: `def : Pat<(i32 0), (i32 X0)>;` As was noted when Lanai made this change (https://reviews.llvm.org/rL288215), attempting to handle the constant 0 in tablegen leads to assertions due to a physical register being used where a virtual register is expected. llvm-svn: 318738
* [RISCV] Support and tests for a variety of additional LLVM IR constructsAlex Bradbury2017-11-2113-0/+1445
| | | | | | | | | | | | | | | | | | | | | | Previous patches primarily ensured that codegen was possible for the standard RISC-V instructions. However, there are a number of IR inputs that wouldn't be appropriately lowered. This patch both adds test cases and supports lowering for a number of these cases: * Improved sext/zext/trunc support * Support for setcc variants that don't map directly to RISC-V instructions * Lowering mul, and hence support for external symbols * addc, adde, subc, sube * mulhs, srem, mulhu, urem, udiv, sdiv * {srl,sra,shl}_parts * brind * br_jt * bswap, ctlz, cttz, ctpop * rotl, rotr * BlockAddress operands Differential Revision: https://reviews.llvm.org/D29938 llvm-svn: 318737
* [RISCV] Implement lowering of ISD::SELECTAlex Bradbury2017-11-212-0/+118
| | | | | | | | | | | | | | Although ISD::SELECT_CC is a more natural match for RISCVISD::SELECT_CC (and ultimately the integer RISC-V conditional branch instructions), we choose to expand ISD::SELECT_CC and lower ISD::SELECT. The appropriate compare+branch will be created in the case where an ISD::SELECT condition value is created by an ISD::SETCC node, which operates on XLen types. Other datatypes such as floating point don't have conditional branch instructions, and lowering ISD::SELECT allows more flexibility for handling these cases. Differential Revision: https://reviews.llvm.org/D29937 llvm-svn: 318735
* [AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount typeYaxun Liu2017-11-211-3/+3
| | | | | | | | | | | | | | | DAGTypeLegalizer::SplitInteger uses default pointer size as shift amount constant type, which causes less performant ISA in amdgcn---amdgiz target since the default pointer type is i64 whereas the desired shift amount type is i32. This patch fixes that by using TLI.getScalarShiftAmountTy in DAGTypeLegalizer::SplitInteger. The X86 change is necessary since splitting i512 requires shifting amount of 256, which cannot be held by i8. Differential Revision: https://reviews.llvm.org/D40148 llvm-svn: 318727
* [SelectionDAG] When promoting the result of a VSELECT, make sure we promote ↵Craig Topper2017-11-201-0/+14
| | | | | | | | | | | | the condition to the SetCC type for the final result type not the original type. Normally this would be cleaned up by promoting the condition operand next. But in the attached case we promoted the result from v2i48 to v2i64 and the condition from v2i1 to v2i48. Then we tried to "promote" the v2i48 condition back to v2i1 because that's what the SetCC result type for v2i64 is on X86 with VLX. But promote is either a NOP or SIGN_EXTEND and this would need a truncation. With the change here we now get the SetCC type of v2i1 when we're handling the result promotion and the operand no longer needs to be promoted itself. Fixes PR35272. llvm-svn: 318706
* [Sparc] efficient pattern for UINT_TO_FP conversionFedor Sergeev2017-11-201-1/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: while investigating performance degradation of imagick benchmark there were found inefficient pattern for UINT_TO_FP conversion. That pattern causes RAW hazard in assembly code. Specifically, uitofp IR operator results in poor assembler : st %i0, [%fp - 952] ldd [%fp - 952], %f0 it stores 32-bit integer register into memory location and then loads 64-bit floating point data from that location. That is exactly RAW hazard case. To optimize that case it is possible to use SPISD::ITOF and SPISD::XTOF for conversion from integer to floating point data type and to use ISD::BITCAST to copy from integer register into floating point register. The fix is to write custom UINT_TO_FP pattern using SPISD::ITOF, SPISD::XTOF, ISD::BITCAST. Patch by Alexey Lapshin Reviewers: fedor.sergeev, jyknight, dcederman, lero_chris Reviewed By: jyknight Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36875 llvm-svn: 318704
* bpf: add a test case for trunc-op optimizationYonghong Song2017-11-201-0/+106
| | | | | | | | | | | | | | | | Commit b5cbc7760ab8 ("[bpf] allow direct and indirect calls") allowed more than one function in the bpf program, and commit 114353884415 ("bpf: fix a bug in trunc-op optimization") fixed a bug in trunc-op optimization which only showed up with more than one function in the bpf program. This patch added a test case for trunc-op optimization for bpf programs with two functions. Reverting commit "bpf: fix a bug in trunc-op optimization" will cause failure for this test case. Signed-off-by: Yonghong Song <yhs@fb.com> llvm-svn: 318695
* Revert "Fix out-of-order stepping behavior in programs with sunk instructions."Paul Robinson2017-11-201-49/+0
| | | | | | | This reverts commit 30419e150cd940893a13b345e85f96053850208f. aka r318679. It caused "sanitizer-windows" bot to fail. llvm-svn: 318684
* Fix out-of-order stepping behavior in programs with sunk instructions.Paul Robinson2017-11-201-0/+49
| | | | | | | | | | | | | | | | MachineSink attempts to place instructions near the basic blocks where they are needed. Once an instruction has been sunk, its location relative to other instructions is no longer consistent with the original source code. In order to ensure correct single-stepping and profiling, the debug location for sunk instructions is either merged with the insertion point or erased if the target successor block is empty. Patch by Matthew Voss! Differential Revision: https://reviews.llvm.org/D39933 llvm-svn: 318679
* [AMDGPU][MC][GFX8][GFX9] Corrected names of integer ↵Dmitry Preobrazhensky2017-11-2048-297/+299
| | | | | | | | | | | | v_{add/addc/sub/subrev/subb/subbrev} See bug 34765: https://bugs.llvm.org//show_bug.cgi?id=34765 Reviewers: tamazov, SamWot, arsenm, vpykhtin Differential Revision: https://reviews.llvm.org/D40088 llvm-svn: 318675
* [MachineCSE] Add new callback for is caller preserved or constant physregsTony Jiang2017-11-202-24/+83
| | | | | | | | | | | | | The instructions addis,addi, bl are used to calculate the address of TLS thread local variables. These TLS access code sequences are generated repeatedly every time the thread local variable is accessed. By communicating to Machine CSE that X2 is guaranteed to have the same value within the same function call (so called Caller Preserved Physical Register), the redundant TLS access code sequences are cleaned up. Differential Revision: https://reviews.llvm.org/D39173 llvm-svn: 318661
* [AMDGPU] Update test r600.amdgpu-alias-analysis.llYaxun Liu2017-11-201-3/+3
| | | | | | | | | | | | | Manually update test r600.amdgpu-alias-analysis.ll for amdgiz environment since it cannot be done by script. The two pointers are swapped in the output because PrintResults in AliasAnalysisEvaluator.cpp sorts the strings obtained from printAsOperand before printing them. Differential Revision: https://reviews.llvm.org/D40131 llvm-svn: 318660
* [mips] Reorder target specific passesSimon Dardis2017-11-201-0/+154
| | | | | | | | | Move the hazard scheduling pass to after the long branch pass, as the long branch pass can create forbiddden slot hazards. Rather than complicating the implementation of the long branch pass to handle forbidden slot hazards, just reorder the passes. llvm-svn: 318657
* [SystemZ] Bugfix for handling of subregisters in getRegAllocationHints().Jonas Paulsson2017-11-201-0/+82
| | | | | | | | The 32 bit subreg indices of GR128 registers must also be checked for in getRC32(). Review: Ulrich Weigand. llvm-svn: 318652
* [PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.Tony Jiang2017-11-2011-60/+105
| | | | | | | | | | | | | | | | | | | | The VSX versions have the advantage of a full 64-register target whereas the FP ones have the advantage of lower latency and higher throughput. So what we’re after is using the faster instructions in low register pressure situations and using the larger register file in high register pressure situations. The heuristic chooses between the following 7 pairs of instructions. PPC::LXSSPX vs PPC::LFSX PPC::LXSDX vs PPC::LFDX PPC::STXSSPX vs PPC::STFSX PPC::STXSDX vs PPC::STFDX PPC::LXSIWAX vs PPC::LFIWAX PPC::LXSIWZX vs PPC::LFIWZX PPC::STXSIWX vs PPC::STFIWX Differential Revision: https://reviews.llvm.org/D38486 llvm-svn: 318651
* [AArch64][TableGen] Skip tied result operands for InstAliasSander de Smalen2017-11-2020-187/+184
| | | | | | | | | | | | | | | | | | | | Summary: This patch fixes an issue so that the right alias is printed when the instruction has tied operands. It checks the number of operands in the resulting instruction as opposed to the alias, and then skips over tied operands that should not be printed in the alias. This allows to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARM Architecture Reference Manual. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Please note that the patch is mostly the same as https://reviews.llvm.org/D29219 which was reverted because of an issue found when running TableGen with the Address Sanitizer. That issue has been addressed in this iteration of the patch. Reviewers: rengolin, stoklund, huntergr, SjoerdMeijer, rovka Reviewed By: rengolin, SjoerdMeijer Subscribers: fhahn, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D40030 llvm-svn: 318650
* AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG ↵Valery Pykhtin2017-11-201-0/+589
| | | | | | | | (experimental) Differential revision: https://reviews.llvm.org/D39897 llvm-svn: 318649
* [ARM GlobalISel] Add test for RSBri. NFCDiana Picus2017-11-201-0/+58
| | | | | | | | Add instruction selector test for RSBri, which is derived from AsI1_rbin_irs, and make sure it doesn't get mistaken for SUBri, which is derived from the very similar AsI1_bin_irs pattern. llvm-svn: 318643
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