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| author | Dylan McKay <me@dylanmckay.io> | 2017-11-24 15:36:43 +0000 |
|---|---|---|
| committer | Dylan McKay <me@dylanmckay.io> | 2017-11-24 15:36:43 +0000 |
| commit | d3972a8f11fe08ead61d94e7313c880acea65bcc (patch) | |
| tree | c607613336b6db360b126ca29b2074236e97c102 /llvm/test/CodeGen | |
| parent | 51ebcaaf258ee206c6e7179a6803ef4e13e32a2e (diff) | |
| download | bcm5719-llvm-d3972a8f11fe08ead61d94e7313c880acea65bcc.tar.gz bcm5719-llvm-d3972a8f11fe08ead61d94e7313c880acea65bcc.zip | |
[AVR] Use the short form of 'clr <reg>'
r318895 made it so that the simpler instruction aliases are printed
rather than their expanded form.
llvm-svn: 318954
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AVR/interrupts.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AVR/mul.ll | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AVR/zext.ll | 10 |
3 files changed, 10 insertions, 10 deletions
diff --git a/llvm/test/CodeGen/AVR/interrupts.ll b/llvm/test/CodeGen/AVR/interrupts.ll index 21f4eca7441..5dddf0ea701 100644 --- a/llvm/test/CodeGen/AVR/interrupts.ll +++ b/llvm/test/CodeGen/AVR/interrupts.ll @@ -7,7 +7,7 @@ define avr_intrcc void @interrupt_handler() { ; CHECK-NEXT: push r1 ; CHECK-NEXT: in r0, 63 ; CHECK-NEXT: push r0 -; CHECK: eor r0, r0 +; CHECK: clr r0 ; CHECK: pop r0 ; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: pop r1 @@ -23,7 +23,7 @@ define avr_signalcc void @signal_handler() { ; CHECK-NEXT: push r1 ; CHECK-NEXT: in r0, 63 ; CHECK-NEXT: push r0 -; CHECK: eor r0, r0 +; CHECK: clr r0 ; CHECK: pop r0 ; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: pop r1 diff --git a/llvm/test/CodeGen/AVR/mul.ll b/llvm/test/CodeGen/AVR/mul.ll index 3756abe3d9b..2f169347c46 100644 --- a/llvm/test/CodeGen/AVR/mul.ll +++ b/llvm/test/CodeGen/AVR/mul.ll @@ -3,7 +3,7 @@ define i8 @mult8(i8 %a, i8 %b) { ; CHECK-LABEL: mult8: ; CHECK: muls r22, r24 -; CHECK: eor r1, r1 +; CHECK: clr r1 ; CHECK: mov r24, r0 %mul = mul i8 %b, %a ret i8 %mul @@ -16,10 +16,10 @@ define i16 @mult16(i16 %a, i16 %b) { ; CHECK: mul r22, r24 ; CHECK: mov r19, r0 ; CHECK: mov r20, r1 -; CHECK: eor r1, r1 +; CHECK: clr r1 ; CHECK: add r20, r18 ; CHECK: muls r23, r24 -; CHECK: eor r1, r1 +; CHECK: clr r1 ; CHECK: mov r22, r0 ; CHECK: add r22, r20 ; :TODO: finish after reworking shift instructions diff --git a/llvm/test/CodeGen/AVR/zext.ll b/llvm/test/CodeGen/AVR/zext.ll index ff7a653c7ef..1f679c9d524 100644 --- a/llvm/test/CodeGen/AVR/zext.ll +++ b/llvm/test/CodeGen/AVR/zext.ll @@ -4,27 +4,27 @@ ; eor R25, R25 define i16 @zext1(i8 %x) { ; CHECK-LABEL: zext1: -; CHECK: eor r25, r25 +; CHECK: clr r25 %1 = zext i8 %x to i16 ret i16 %1 } ; zext R25:R24, R20 ; mov R24, R20 -; eor R25, R25 +; clr R25 define i16 @zext2(i8 %x, i8 %y) { ; CHECK-LABEL: zext2: ; CHECK: mov r24, r22 -; CHECK: eor r25, r25 +; CHECK: clr r25 %1 = zext i8 %y to i16 ret i16 %1 } ; zext R25:R24, R24 -; eor R25, R25 +; clr R25 define i16 @zext_i1(i1 %x) { ; CHECK-LABEL: zext_i1: -; CHECK: eor r25, r25 +; CHECK: clr r25 %1 = zext i1 %x to i16 ret i16 %1 } |

