summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen
Commit message (Expand)AuthorAgeFilesLines
* [CodeGen] Use MIR syntax for MachineMemOperand printingFrancis Visoiu Mistrih2018-03-1415-47/+47
* [X86] Add haswell testing for PR35635 as well.Simon Pilgrim2018-03-141-16/+34
* [AArch64] Emit CSR loads in the same order as storesFrancis Visoiu Mistrih2018-03-141-0/+72
* [X86] Add back fast-isel code for handling i8 shifts.Craig Topper2018-03-141-0/+12
* [AArch64] Keep track of MIFlags in the LoadStoreOptimizerFrancis Visoiu Mistrih2018-03-141-0/+99
* [X86] Teach X86TargetLowering::targetShrinkDemandedConstant to set non-demand...Craig Topper2018-03-143-11/+18
* [X86][AVX] Use WriteFShuffleLd for broadcast reg-mem instructionsSimon Pilgrim2018-03-142-10/+10
* SjLjEHPrepare: Don't reg-to-mem swifterror valuesArnold Schwaighofer2018-03-141-2/+31
* [GlobalIsel][X86] Support for G_SDIV instructionAlexander Ivchenko2018-03-145-0/+607
* [X86][Btver2] Fix YMM shuffle, permute and permutevar scheduler costsSimon Pilgrim2018-03-142-15/+15
* [X86][SSE] Use WriteFShuffleLd for MOVDDUP/MOVSHDUP/MOVSLDUP reg-mem instruct...Simon Pilgrim2018-03-142-15/+18
* [AArch64] Don't produce R_AARCH64_TLSLE_LDST32_TPREL_LO12_NCMartin Storsjo2018-03-141-2/+3
* [GlobalISel][X86] Support G_LSHR/G_ASHR/G_SHLAlexander Ivchenko2018-03-1413-13/+2331
* [GlobalIsel][X86] Support for G_ZEXT instructionAlexander Ivchenko2018-03-143-0/+812
* [X86] Re-generate test to get proper capitalization of its CHECK lines. NFCCraig Topper2018-03-131-41/+41
* [X86] Rewrite LowerAVXCONCAT_VECTORS similar to how we handle vXi1 concats.Craig Topper2018-03-132-6/+0
* [DAGCombiner] Allow visitEXTRACT_SUBVECTOR to combine with BUILD_VECTORS betw...Craig Topper2018-03-137-165/+190
* [MIR] Allow frame-setup and frame-destroy on the same instructionFrancis Visoiu Mistrih2018-03-131-0/+4
* [x86] add test for WriteZero sched class instructions; NFCSanjay Patel2018-03-131-0/+92
* [DAGCombine] visitREM - Don't assume that one divrem isn't driving anotherSimon Pilgrim2018-03-131-0/+30
* [X86][Btver2] Split i8/i16/i32/i64 div/idiv costsSimon Pilgrim2018-03-131-14/+14
* [mips] Fix the definitions of the EVA instructionsSimon Dardis2018-03-131-2/+2
* [mips] Don't create nested CALLSEQ_START..CALLSEQ_END nodes.Simon Dardis2018-03-131-0/+430
* [X86][SSE41] createVariablePermute v2X64 - PCMPEQQ can test for index 0/1 and...Simon Pilgrim2018-03-131-15/+14
* [CodeGenPrepare] Respect endianness in splitMergedValStore.Jonas Paulsson2018-03-131-0/+22
* bpf: Extends zero extension elimination beyond comparison instructionsYonghong Song2018-03-131-0/+16
* bpf: J*_RR should check both operandsYonghong Song2018-03-131-0/+20
* bpf: Tighten subregister definition checkYonghong Song2018-03-131-1/+32
* bpf: Add more check directives in peephole testcaseYonghong Song2018-03-131-0/+4
* [LegalizeTypes] In SplitVecOp_TruncateHelper, use GetSplitVector on the input...Craig Topper2018-03-131-328/+165
* [AArch64] Fold adds with tprel_lo12_nc and secrel_lo12 into a following ldr/strMartin Storsjo2018-03-122-15/+6
* [Hexagon] Fix typo in testcaseKrzysztof Parzyszek2018-03-121-1/+1
* [Hexagon] Counting leading/trailing bits is cheapKrzysztof Parzyszek2018-03-121-0/+75
* [Hexagon] Subtarget feature to emit one instruction per packetKrzysztof Parzyszek2018-03-122-0/+109
* [AMDGPU] Fix lowering enqueue kernel when kernel has no nameYaxun Liu2018-03-121-9/+47
* [Hexagon] Add REQUIRES: asserts to testcases that use -statsKrzysztof Parzyszek2018-03-122-0/+2
* [Hexagon] Add REQUIRES: asserts to testcases that use -debug-onlyKrzysztof Parzyszek2018-03-123-1/+3
* [AMDGPU][MC] Corrected GATHER4 opcodesDmitry Preobrazhensky2018-03-122-56/+0
* [Hexagon] Add more lit testsKrzysztof Parzyszek2018-03-12386-0/+32789
* AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELTMatt Arsenault2018-03-124-0/+392
* AMDGPU/GlobalISel: InstrMapping for G_MERGE_VALUESMatt Arsenault2018-03-122-1/+45
* AMDGPU/GlobalISel: Make some G_MERGE_VALUEs legalMatt Arsenault2018-03-122-0/+147
* [X86][SSE] createVariablePermute - PSHUFB requires SSSE3 not just SSE3Simon Pilgrim2018-03-121-14/+455
* [X86][MMX] Support MMX build vectors to avoid SSE usage (PR29222)Simon Pilgrim2018-03-114-1650/+565
* [X86][AVX512] Added more non-VLX test casesSimon Pilgrim2018-03-112-264/+197
* [X86][AVX] createVariablePermute - scale v16i16 variable permutes to use v32i...Simon Pilgrim2018-03-111-560/+103
* [X86][AVX] createVariablePermute - widen permutes for cases where the source ...Simon Pilgrim2018-03-112-83/+100
* [X86][AVX] createVariablePermute - use PSHUFB+PCMPGT+SELECT for v32i8 variabl...Simon Pilgrim2018-03-111-1198/+73
* [X86][AVX] createVariablePermute - use 2xVPERMIL+PCMPGT+SELECT for v8i32/v8f3...Simon Pilgrim2018-03-111-240/+132
* [X86][AVX512] createVariablePermute - Non-VLX targets can widen v4i64/v8f64 v...Simon Pilgrim2018-03-111-72/+28
OpenPOWER on IntegriCloud