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authorCraig Topper <craig.topper@intel.com>2018-03-14 16:55:15 +0000
committerCraig Topper <craig.topper@intel.com>2018-03-14 16:55:15 +0000
commitb36cb20ef9eadc49eac534e9b3999b6d9243d81c (patch)
tree8bec7ecf759f796d71613915b4c724ebb8b41e7f /llvm/test/CodeGen
parente392ce43157f250859be13eb236fd2a7f7697903 (diff)
downloadbcm5719-llvm-b36cb20ef9eadc49eac534e9b3999b6d9243d81c.tar.gz
bcm5719-llvm-b36cb20ef9eadc49eac534e9b3999b6d9243d81c.zip
[X86] Teach X86TargetLowering::targetShrinkDemandedConstant to set non-demanded bits if it helps created an and mask that can be matched as a zero extend.
I had to modify the bswap recognition to allow unshrunk masks to make this work. Fixes PR36689. Differential Revision: https://reviews.llvm.org/D44442 llvm-svn: 327530
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/X86/pr12360.ll6
-rw-r--r--llvm/test/CodeGen/X86/pr32284.ll7
-rw-r--r--llvm/test/CodeGen/X86/zext-demanded.ll16
3 files changed, 18 insertions, 11 deletions
diff --git a/llvm/test/CodeGen/X86/pr12360.ll b/llvm/test/CodeGen/X86/pr12360.ll
index 73dd4966dbb..6ffa2fc5de6 100644
--- a/llvm/test/CodeGen/X86/pr12360.ll
+++ b/llvm/test/CodeGen/X86/pr12360.ll
@@ -45,9 +45,9 @@ entry:
define zeroext i1 @f4(i32 %x) {
; CHECK-LABEL: f4:
; CHECK: ## %bb.0: ## %entry
-; CHECK-NEXT: shrl $15, %edi
-; CHECK-NEXT: andl $1, %edi
-; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: movzwl %di, %eax
+; CHECK-NEXT: shrl $15, %eax
+; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/pr32284.ll b/llvm/test/CodeGen/X86/pr32284.ll
index 62e7a66a0f1..44367cbdaa8 100644
--- a/llvm/test/CodeGen/X86/pr32284.ll
+++ b/llvm/test/CodeGen/X86/pr32284.ll
@@ -514,8 +514,6 @@ define void @f3() #0 {
; 686-O0-NEXT: movl %ecx, %edi
; 686-O0-NEXT: xorl %esi, %edi
; 686-O0-NEXT: andl %edi, %eax
-; 686-O0-NEXT: movb %al, %dl
-; 686-O0-NEXT: movzbl %dl, %eax
; 686-O0-NEXT: orl %eax, %ecx
; 686-O0-NEXT: movl %ecx, (%esp)
; 686-O0-NEXT: movl $0, {{[0-9]+}}(%esp)
@@ -545,9 +543,8 @@ define void @f3() #0 {
; 686-NEXT: movl var_16, %edx
; 686-NEXT: xorl %ecx, %edx
; 686-NEXT: andl %eax, %edx
-; 686-NEXT: movzbl %dl, %eax
-; 686-NEXT: orl %ecx, %eax
-; 686-NEXT: movl %eax, (%esp)
+; 686-NEXT: orl %ecx, %edx
+; 686-NEXT: movl %edx, (%esp)
; 686-NEXT: movl $0, {{[0-9]+}}(%esp)
; 686-NEXT: movl %ecx, var_46
; 686-NEXT: movl %ebp, %esp
diff --git a/llvm/test/CodeGen/X86/zext-demanded.ll b/llvm/test/CodeGen/X86/zext-demanded.ll
index c292b0bc1dc..acfe8f42df9 100644
--- a/llvm/test/CodeGen/X86/zext-demanded.ll
+++ b/llvm/test/CodeGen/X86/zext-demanded.ll
@@ -76,9 +76,8 @@ define i32 @test6(i32 %x) {
define i32 @test7(i32 %x) {
; CHECK-LABEL: test7:
; CHECK: # %bb.0:
-; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
-; CHECK-NEXT: andl $65534, %edi # imm = 0xFFFE
-; CHECK-NEXT: leal 1(%rdi), %eax
+; CHECK-NEXT: orl $1, %edi
+; CHECK-NEXT: movzwl %di, %eax
; CHECK-NEXT: retq
%y = and i32 %x, 65534
%z = or i32 %y, 1
@@ -138,3 +137,14 @@ define i64 @mul_neg_one(i64 %x) {
ret i64 %r
}
+define i32 @PR36689(i32*) {
+; CHECK-LABEL: PR36689:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movzwl (%rdi), %eax
+; CHECK-NEXT: orl $255, %eax
+; CHECK-NEXT: retq
+ %2 = load i32, i32* %0
+ %3 = and i32 %2, 65280
+ %4 = or i32 %3, 255
+ ret i32 %4
+}
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