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* NFC - Typo fixes in X86 flags-copy-lowering.mir testGabor Buella2018-07-071-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D48934 llvm-svn: 336484
* [MachineOutliner] Add missing liveness tracking info in MIR test.Yvan Roux2018-07-071-0/+1
| | | | | | This should bring the bots back to green state. llvm-svn: 336482
* Revert 336426 (and follow-ups 428, 440), it very likely caused PR38084.Nico Weber2018-07-063-213/+20
| | | | llvm-svn: 336453
* [ARM] ParallelDSP: added statistics, NFC.Sjoerd Meijer2018-07-0613-17/+18
| | | | | | | | | Added statistics for the number of SMLAD instructions created, and als renamed the pass name to -arm-parallel-dsp. Differential Revision: https://reviews.llvm.org/D48971 llvm-svn: 336441
* Commit rL336426 cause buildbot failuresDiogo N. Sampaio2018-07-062-6/+6
| | | | | | | | http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/50537/testReport/junit/LLVM/CodeGen_AArch64/FoldRedundantShiftedMasking_ll/ This removes the comments of the function label causing this error. llvm-svn: 336440
* [SelectionDAG] https://reviews.llvm.org/D48278Diogo N. Sampaio2018-07-063-20/+213
| | | | | | | | | | | | | | | | D48278 Allow to reduce redundant shift masks. For example: x1 = x & 0xAB00 x2 = (x >> 8) & 0xAB can be reduced to: x1 = x & 0xAB00 x2 = x1 >> 8 It only allows folding when the masks and shift values are constants. llvm-svn: 336426
* [X86] Remove FMA4 scalar intrinsics. Use llvm.fma intrinsic instead.Craig Topper2018-07-063-16/+28
| | | | | | | | The intrinsics can be implemented with a f32/f64 llvm.fma intrinsic and an insert into a zero vector. There are a couple regressions here due to SelectionDAG not being able to pull an fneg through an extract_vector_elt. I'm not super worried about this though as InstCombine should be able to do it before we get to SelectionDAG. llvm-svn: 336416
* [X86] Remove all of the avx512 masked packed fma intrinsics. Use llvm.fma or ↵Craig Topper2018-07-063-356/+1967
| | | | | | | | | | unmasked 512-bit intrinsics with rounding mode. This upgrades all of the intrinsics to use fneg instructions to convert fma into fmsub/fnmsub/fnmadd/fmsubadd. And uses a select instruction for masking. This matches how clang uses the intrinsics these days. llvm-svn: 336409
* [X86] Cleanup some of the avx512 masked fma tests to prepare for removing ↵Craig Topper2018-07-063-1217/+1099
| | | | | | | | | | and autoupgrading. -Split cases that call 2 intrinsics in the same case. -Remove testing mask3 and maskz intrinsics with an all ones mask. These won't be interesting after the upgrade. -Restore test cases for some intrinsics that are marked for deletion, but haven't been deleted yet. llvm-svn: 336408
* [Power9] Add __float128 library call for fremStefan Pintilie2018-07-061-0/+14
| | | | | | | | Power 9 does not have a hardware instruction for frem but we can call fmodf128. Differential Revision: https://reviews.llvm.org/D48552 llvm-svn: 336406
* [x86]Add a test case to show missed vfnmadd generation.Easwaran Raman2018-07-061-0/+25
| | | | llvm-svn: 336404
* [X86] Remove the last of the 'x86.fma.' intrinsics and autoupgrade them to ↵Craig Topper2018-07-054-184/+1586
| | | | | | | | 'llvm.fma'. Add upgrade tests for all. Still need to remove the AVX512 masked versions. llvm-svn: 336383
* [X86] Add SHUF128 to target shuffle decoding.Craig Topper2018-07-052-65/+127
| | | | | | Differential Revision: https://reviews.llvm.org/D48954 llvm-svn: 336376
* AMDGPU: Don't use spir_kernel in a testMatt Arsenault2018-07-051-3/+2
| | | | | | Also use verify-machineinstrs. llvm-svn: 336374
* AMDGPU/GlobalISel: Implement custom kernel arg loweringMatt Arsenault2018-07-052-20/+789
| | | | | | | | | | | | | Avoid using allocateKernArg / AssignFn. We do not want any of the type splitting properties of normal calling convention lowering. For now at least this exists alongside the IR argument lowering pass. This is necessary to handle struct padding correctly while some arguments are still skipped by the IR argument lowering pass. llvm-svn: 336373
* [Power9] Add lib calls for float128 operations with no equivalent PPC ↵Lei Huang2018-07-051-1/+146
| | | | | | | | | | | instructions Map the following instructions to the proper float128 lib calls: pow[i], exp[2], log[2|10], sin, cos, fmin, fmax Differential Revision: https://reviews.llvm.org/D48544 llvm-svn: 336361
* [X86][SSE] Add srem x, (1 << c) combine testsSimon Pilgrim2018-07-051-0/+227
| | | | | | Now that D45806 has landed we can start trying to avoid scalarizing srem by constant - these tests demonstrate some example cases. llvm-svn: 336360
* [AArch64, PowerPC, x86] add tests for signbit bit hacks; NFCSanjay Patel2018-07-053-0/+459
| | | | llvm-svn: 336348
* [AMDGPU] Add VALU to V_INTERP InstructionsRyan Taylor2018-07-051-0/+19
| | | | | | | | | | | | Wait states are not properly being inserted after buffer_store for v_interp instructions. Add VALU to V_INTERP instructions so that the GCNHazardRecognizer can check and insert the appropriate wait states when needed. Differential Revision: https://reviews.llvm.org/D48772 Change-Id: Id540c9b074fc69b5c1de6b182276aa089c74aa64 llvm-svn: 336339
* Partially revert r336268 in address-offsets.llKrasimir Georgiev2018-07-051-40/+40
| | | | | | | | | | | | | | Summary: There the typos are intentional, explicitly introduced to disable these cases in r280285. Reviewers: bkramer Reviewed By: bkramer Subscribers: dschuff, sbc100, jgravelle-google, aheejin, llvm-commits Differential Revision: https://reviews.llvm.org/D48962 llvm-svn: 336336
* [X86][SSE] Add extra v16i16 shl x,c -> pmullw testSimon Pilgrim2018-07-051-0/+27
| | | | | | We want to compare shifts with repeated vs non-repeated v8i16 shuffle masks (for PBLENDW ymm) llvm-svn: 336333
* [mips] Fix atomic operations at O0, v3Aleksandar Beserminji2018-07-054-428/+9037
| | | | | | | | | | | | | | | | | | | | | | | Similar to PR/25526, fast-regalloc introduces spills at the end of basic blocks. When this occurs in between an ll and sc, the stores can cause the atomic sequence to fail. This patch fixes the issue by introducing more pseudos to represent atomic operations and moving their lowering to after the expansion of postRA pseudos. This version addresses issues with the initial implementation and covers all atomic operations. This resolves PR/32020. Thanks to James Cowgill for reporting the issue! Patch By: Simon Dardis Differential Revision: https://reviews.llvm.org/D31287 llvm-svn: 336328
* [NEON] Fix combining of vldx_dup intrinsics with updating of base addressesIvan A. Kosarev2018-07-051-0/+43
| | | | | | | | | | | | | Resolves: Unsupported ARM Neon intrinsics in Target-specific DAG combine function for VLDDUP https://bugs.llvm.org/show_bug.cgi?id=38031 Related diff: D48439 Differential Revision: https://reviews.llvm.org/D48920 llvm-svn: 336325
* Partial revert of "NFC - Various typo fixes in tests"Mikael Holmen2018-07-053-15/+19
| | | | | | | | This partially reverts r336268 since it causes buildbot failures. Added FIXME at the places where the CHECKs are misspelled. llvm-svn: 336323
* [ARM] ParallelDSP: only support i16 loads for nowSjoerd Meijer2018-07-051-1/+46
| | | | | | | | | We were miscompiling i8 loads, so reject them as unsupported narrow operations for now. Differential Revision: https://reviews.llvm.org/D48944 llvm-svn: 336319
* [Power9] Optimize codgen for conversions of int to float128Lei Huang2018-07-052-10/+136
| | | | | | | | | | | | Optimize code sequences for integer conversion to fp128 when the integer is a result of: * float->int * float->long * double->int * double->long Differential Revision: https://reviews.llvm.org/D48429 llvm-svn: 336316
* [X86] Remove X86 specific scalar FMA intrinsics and upgrade to tart ↵Craig Topper2018-07-054-88/+104
| | | | | | independent FMA and extractelement/insertelement. llvm-svn: 336315
* [Power9][NFC] add back-end tests for passing homogeneous fp128 aggregates by ↵Lei Huang2018-07-051-3/+187
| | | | | | | | | | | value Tests to verify that we are passing fp128 via VSX registers as per ABI. These are related to clang commit rL336308. Differential Revision: https://reviews.llvm.org/D48310 llvm-svn: 336314
* [Power9] Add tests for passing float128 in VSX reg for non-homogenous aggregatesLei Huang2018-07-051-0/+206
| | | | | | Add missing testcase for rL336310 llvm-svn: 336313
* [Power9]Legalize and emit code for quad-precision convert from single-precisionLei Huang2018-07-052-27/+162
| | | | | | | | | Legalize and emit code for quad-precision floating point operation conversion of single-precision value to quad-precision. Differential Revision: https://reviews.llvm.org/D47569 llvm-svn: 336307
* [Power9] Implement float128 parameter passing and return valuesLei Huang2018-07-051-0/+268
| | | | | | | | | | This patch enable parameter passing and return by value for float128 types. Passing aggregate/union which contain float128 members will be submitted in subsequent patches. Differential Revision: https://reviews.llvm.org/D47552 llvm-svn: 336306
* [X86] Add support for combining FMSUB/FNMADD/FNMSUB ISD nodes with an fneg ↵Craig Topper2018-07-053-38/+14
| | | | | | | | | | input. Previously we could only negate the FMADD opcodes. This used to be mostly ok when we lowered FMA intrinsics during lowering. But with the move to llvm.fma from target specific intrinsics, we can combine (fneg (fma)) to (fmsub) earlier. So if we start with (fneg (fma (fneg))) we would get stuck at (fmsub (fneg)). This patch fixes that so we can also combine things like (fmsub (fneg)). llvm-svn: 336304
* [X86] Remove some of the packed FMA3 intrinsics since we no longer use them ↵Craig Topper2018-07-052-6/+18
| | | | | | | | | | in clang. There's a regression in here due to inability to combine fneg inputs of X86ISD::FMSUB/FNMSUB/FNMADD nodes. More removals to come, but I wanted to stop and fix the regression that showed up in this first. llvm-svn: 336303
* [Power9]Legalize and emit code for round & convert quad-precision valuesLei Huang2018-07-041-0/+154
| | | | | | | | | Legalize and emit code for round & convert float128 to double precision and single precision. Differential Revision: https://reviews.llvm.org/D46997 llvm-svn: 336299
* [mips] Warn when crc, ginv, virt flags are used with too old revisionVladimir Stefanovic2018-07-041-0/+45
| | | | | | | | | CRC and GINV ASE require revision 6, Virtualization requires revision 5. Print a warning when revision is older than required. Differential Revision: https://reviews.llvm.org/D48843 llvm-svn: 336296
* [PowerPC] Replace the Post RA List Scheduler with the Machine SchedulerStefan Pintilie2018-07-0476-482/+457
| | | | | | | | | | | We want to run the Machine Scheduler instead of the List Scheduler after RA. Checked with a performance run on a Power 9 machine with SPEC 2006 and while some benchmarks improved and others degraded the geomean was slightly improved with the Machine Scheduler. Differential Revision: https://reviews.llvm.org/D45265 llvm-svn: 336295
* [X86][SSE] Add v16i16 shl x,c -> pmullw testSimon Pilgrim2018-07-041-3/+26
| | | | llvm-svn: 336277
* [X86][SSE] Add SSE2 target to some shift testsSimon Pilgrim2018-07-043-275/+638
| | | | | | | | Show the difference in behaviour cf SSE41 (no PMULLD, PBLENDW etc.) Raised by D48936 llvm-svn: 336271
* NFC - Various typo fixes in testsGabor Buella2018-07-0416-77/+77
| | | | llvm-svn: 336268
* [X86][SSE] Blend any v8i16/v4i32 shift with 2 shift unique values (REAPPLIED)Simon Pilgrim2018-07-041-22/+12
| | | | | | | | We were only doing this for basic blends, despite shuffle lowering now being good enough to handle more complex blends. This means that the two v8i16 splat shifts are performed in parallel instead of serially as the general shift case. Reapplied with a fixed (extra null tests) version of rL336113 after reversion in rL336189 - extra test case added at rL336247. llvm-svn: 336250
* [X86][SSE] Add reduced crash test case for r336113 - [X86][SSE] Blend any ↵Simon Pilgrim2018-07-041-0/+25
| | | | | | | | v8i16/v4i32 shift with 2 shift unique values The patch was reverted at r336189 due to crashes llvm-svn: 336247
* [ImplicitNullChecks] Check for rewrite of register used in 'test' instructionMax Kazantsev2018-07-041-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | The following code pattern: mov %rax, %rcx test %rax, %rax %rax = .... je throw_npe mov(%rcx), %r9 mov(%rax), %r10 gets transformed into the following incorrect code after implicit null check pass: mov %rax, %rcx %rax = .... faulting_load_op("movl (%rax), %r10", throw_npe) mov(%rcx), %r9 For implicit null check pass, if the register that is checked for null value (ie, the register used in the 'test' instruction) is written into before the condition jump, we should avoid doing the optimization. Patch by Surya Kumari Jangala! Differential Revision: https://reviews.llvm.org/D48627 Reviewed By: skatkov llvm-svn: 336241
* [NVPTX] Expand v2f16 INSERT_VECTOR_ELTBenjamin Kramer2018-07-031-0/+8
| | | | | | Vectorization can create them. llvm-svn: 336227
* [X86] Add tests for low/high bit clearing with different attributes.Roman Lebedev2018-07-032-0/+2776
| | | | | | | | | | | | | | D48768 may turn some of these into shifts. Reviewers: spatel Reviewed By: spatel Subscribers: spatel, RKSimon, llvm-commits, craig.topper Differential Revision: https://reviews.llvm.org/D48767 llvm-svn: 336224
* [X86][AsmParser] Don't consider %eip as a valid register outside of 32-bit mode.Craig Topper2018-07-031-1/+1
| | | | | | | | This might make the error message added in r335668 unneeded, but I'm not sure yet. The check for RIP is technically unnecessary since RIP is in GR64, but that fact is kind of surprising so be explicit. llvm-svn: 336217
* [AArch64][GlobalISel] Fix fallbacks introduced in r336120 due to ↵Amara Emerson2018-07-032-4/+8
| | | | | | | | | | unselectable stores. r336120 resulted in falling back to SelectionDAG more often due to the G_STORE MMOs not matching the vreg size. This fixes that by explicitly any-extending the value. llvm-svn: 336209
* [DAGCombiner] visitSDIV - Permit MIN_SIGNED_VALUE in pow2 vector codegenSimon Pilgrim2018-07-031-177/+206
| | | | | | Now that D45806 has landed, we can re-enable support for MIN_SIGNED_VALUE in the sdiv by pow2-constant code llvm-svn: 336198
* Revert "[X86][SSE] Blend any v8i16/v4i32 shift with 2 shift unique values"Benjamin Kramer2018-07-031-12/+22
| | | | | | This reverts commit r336113. It causes crashes. llvm-svn: 336189
* [MIPS GlobalISel] Lower arguments using stackPetar Jovanovic2018-07-031-0/+33
| | | | | | | | | | | Lower more than 4 arguments using stack. This patch targets MIPS32. It supports only functions with arguments of type i32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D47934 llvm-svn: 336185
* [X86] Add avx512vl command line to break-false-dep.llCraig Topper2018-07-031-2/+23
| | | | llvm-svn: 336169
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