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| author | Ivan A. Kosarev <ikosarev@accesssoftek.com> | 2018-07-05 08:59:49 +0000 |
|---|---|---|
| committer | Ivan A. Kosarev <ikosarev@accesssoftek.com> | 2018-07-05 08:59:49 +0000 |
| commit | 466037900c34e2d2727e8688088f8d2b9eef81bd (patch) | |
| tree | fa8d8c38959474444797b7b87dbb56dd7413b56f /llvm/test/CodeGen | |
| parent | 097ab704c9c43a85e918d6c2c9366e08b677b91d (diff) | |
| download | bcm5719-llvm-466037900c34e2d2727e8688088f8d2b9eef81bd.tar.gz bcm5719-llvm-466037900c34e2d2727e8688088f8d2b9eef81bd.zip | |
[NEON] Fix combining of vldx_dup intrinsics with updating of base addresses
Resolves:
Unsupported ARM Neon intrinsics in Target-specific DAG combine
function for VLDDUP
https://bugs.llvm.org/show_bug.cgi?id=38031
Related diff: D48439
Differential Revision: https://reviews.llvm.org/D48920
llvm-svn: 336325
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/ARM/arm-vlddup-update.ll | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/arm-vlddup-update.ll b/llvm/test/CodeGen/ARM/arm-vlddup-update.ll new file mode 100644 index 00000000000..c39dfc764dd --- /dev/null +++ b/llvm/test/CodeGen/ARM/arm-vlddup-update.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -verify-machineinstrs \ +; RUN: -asm-verbose=false | FileCheck %s + +%struct.uint32x2x2_t = type { <2 x i32>, <2 x i32> } +%struct.uint32x2x3_t = type { <2 x i32>, <2 x i32>, <2 x i32> } +%struct.uint32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } + +declare %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0i8(i8*, i32) +declare %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0i8(i8*, i32) +declare %struct.uint32x2x4_t @llvm.arm.neon.vld4dup.v2i32.p0i8(i8*, i32) + +; CHECK-LABEL: test_vld2_dup_update +; CHECK: vld2.32 {d16[], d17[]}, {{\[}}[[SRC_R:r[0-9]+]]] +; CHECK: add {{r[0-9]+|lr}}, [[SRC_R]], #4 +define i8* @test_vld2_dup_update(%struct.uint32x2x2_t* %dest, i8* %src) { +entry: + %tmp = tail call %struct.uint32x2x2_t @llvm.arm.neon.vld2dup.v2i32.p0i8(i8* %src, i32 4) + store %struct.uint32x2x2_t %tmp, %struct.uint32x2x2_t* %dest, align 8 + %updated_src = getelementptr inbounds i8, i8* %src, i32 4 + ret i8* %updated_src +} + +; CHECK-LABEL: test_vld3_dup_update +; CHECK: vld3.32 {d16[], d17[], d18[]}, {{\[}}[[SRC_R:r[0-9]+]]] +; CHECK: add {{r[0-9]+|lr}}, [[SRC_R]], #4 +define i8* @test_vld3_dup_update(%struct.uint32x2x3_t* %dest, i8* %src) { +entry: + %tmp = tail call %struct.uint32x2x3_t @llvm.arm.neon.vld3dup.v2i32.p0i8(i8* %src, i32 4) + store %struct.uint32x2x3_t %tmp, %struct.uint32x2x3_t* %dest, align 8 + %updated_src = getelementptr inbounds i8, i8* %src, i32 4 + ret i8* %updated_src +} + +; CHECK-LABEL: test_vld4_dup_update +; CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, {{\[}}[[SRC_R:r[0-9]+]]] +; CHECK: add {{r[0-9]+|lr}}, [[SRC_R]], #4 +define i8* @test_vld4_dup_update(%struct.uint32x2x4_t* %dest, i8* %src) { +entry: + %tmp = tail call %struct.uint32x2x4_t @llvm.arm.neon.vld4dup.v2i32.p0i8(i8* %src, i32 4) + store %struct.uint32x2x4_t %tmp, %struct.uint32x2x4_t* %dest, align 8 + %updated_src = getelementptr inbounds i8, i8* %src, i32 4 + ret i8* %updated_src +} |

