[ARM] ParallelDSP: added statistics, NFC.

Added statistics for the number of SMLAD instructions created, and
als renamed the pass name to -arm-parallel-dsp.

Differential Revision: https://reviews.llvm.org/D48971

llvm-svn: 336441

13 files changed, 18 insertions, 17 deletions

diff --git a/llvm/test/CodeGen/ARM/smlad0.ll b/llvm/test/CodeGen/ARM/smlad0.ll
index 565e4fa5c26..d19a9e534fc 100644
--- a/llvm/test/CodeGen/ARM/smlad0.ll
+++ b/llvm/test/CodeGen/ARM/smlad0.ll
@@ -1,10 +1,10 @@
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
 ;
 ; The Cortex-M0 does not support unaligned accesses:
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m0 < %s -parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m0 < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
 ;
 ; Check DSP extension:
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 -mattr=-dsp < %s -parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 -mattr=-dsp < %s -arm-parallel-dsp -S | FileCheck %s --check-prefix=CHECK-UNSUPPORTED
 ;
 ; CHECK:  %mac1{{\.}}026 = phi i32 [ [[V8:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ]
 ; CHECK:  [[V4:%[0-9]+]] = bitcast i16* %arrayidx3 to i32*
diff --git a/llvm/test/CodeGen/ARM/smlad1.ll b/llvm/test/CodeGen/ARM/smlad1.ll
index 5a504ec1b37..60179f22374 100644
--- a/llvm/test/CodeGen/ARM/smlad1.ll
+++ b/llvm/test/CodeGen/ARM/smlad1.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
 
 ; CHECK-LABEL: @test1
 ; CHECK:  %mac1{{\.}}026 = phi i32 [ [[V8:%[0-9]+]], %for.body ], [ 0, %for.body.preheader ]
diff --git a/llvm/test/CodeGen/ARM/smlad10.ll b/llvm/test/CodeGen/ARM/smlad10.ll
index 7c28eb278d9..904b62a6526 100644
--- a/llvm/test/CodeGen/ARM/smlad10.ll
+++ b/llvm/test/CodeGen/ARM/smlad10.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
 ;
 ; Reduction statement is an i64 type: we only support i32 so check that the
 ; rewrite isn't triggered.
diff --git a/llvm/test/CodeGen/ARM/smlad11.ll b/llvm/test/CodeGen/ARM/smlad11.ll
index a503818384d..04586e66930 100644
--- a/llvm/test/CodeGen/ARM/smlad11.ll
+++ b/llvm/test/CodeGen/ARM/smlad11.ll
@@ -1,4 +1,5 @@
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s
+; REQUIRES: asserts
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S -stats 2>&1 | FileCheck %s
 ;
 ; A more complicated chain: 4 mul operations, so we expect 2 smlad calls.
 ;
@@ -15,9 +16,10 @@
 ; CHECK:  [[V17:%[0-9]+]] = call i32 @llvm.arm.smlad(i32 [[V14]], i32 [[V16]], i32 [[V12]])
 ;
 ; And we don't want to see a 3rd smlad:
-;
 ; CHECK-NOT: call i32 @llvm.arm.smlad
 ;
+; CHECK:  2 arm-parallel-dsp - Number of smlad instructions generated
+;
 define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
 entry:
   %cmp52 = icmp sgt i32 %arg, 0
diff --git a/llvm/test/CodeGen/ARM/smlad12.ll b/llvm/test/CodeGen/ARM/smlad12.ll
index 391ce5c22fd..d4e09ca3fbb 100644
--- a/llvm/test/CodeGen/ARM/smlad12.ll
+++ b/llvm/test/CodeGen/ARM/smlad12.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
 ;
 ; The loop header is not the loop latch.
 ;
diff --git a/llvm/test/CodeGen/ARM/smlad2.ll b/llvm/test/CodeGen/ARM/smlad2.ll
index 219b55c6d6d..e30527ededd 100644
--- a/llvm/test/CodeGen/ARM/smlad2.ll
+++ b/llvm/test/CodeGen/ARM/smlad2.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
 ;
 ; Operands of both muls are not symmetrical (see also comments inlined below), check
 ; that the rewrite isn't triggered.
@@ -49,4 +49,3 @@ for.body:
   %exitcond = icmp ne i32 %add, %arg
   br i1 %exitcond, label %for.body, label %for.cond.cleanup
 }
-
diff --git a/llvm/test/CodeGen/ARM/smlad3.ll b/llvm/test/CodeGen/ARM/smlad3.ll
index 5584c8302cf..875933b609b 100644
--- a/llvm/test/CodeGen/ARM/smlad3.ll
+++ b/llvm/test/CodeGen/ARM/smlad3.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
 ;
 ; The loads are not consecutive: check that the rewrite isn't triggered.
 ;
diff --git a/llvm/test/CodeGen/ARM/smlad4.ll b/llvm/test/CodeGen/ARM/smlad4.ll
index defce8a09b4..20571e3c24a 100644
--- a/llvm/test/CodeGen/ARM/smlad4.ll
+++ b/llvm/test/CodeGen/ARM/smlad4.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
 ;
 ; The loads are not narrow loads: check that the rewrite isn't triggered.
 ;
diff --git a/llvm/test/CodeGen/ARM/smlad5.ll b/llvm/test/CodeGen/ARM/smlad5.ll
index f1e5e722fdd..51a7cad2a1e 100644
--- a/llvm/test/CodeGen/ARM/smlad5.ll
+++ b/llvm/test/CodeGen/ARM/smlad5.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
 ;
 ; The loads are volatile loads: check that the rewrite isn't triggered.
 ;
diff --git a/llvm/test/CodeGen/ARM/smlad6.ll b/llvm/test/CodeGen/ARM/smlad6.ll
index 831cbfd97ac..421036ecfc0 100644
--- a/llvm/test/CodeGen/ARM/smlad6.ll
+++ b/llvm/test/CodeGen/ARM/smlad6.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
 ;
 ; Alias check: check that the rewrite isn't triggered when there's a store
 ; instruction possibly aliasing any mul load operands; arguments are passed
diff --git a/llvm/test/CodeGen/ARM/smlad7.ll b/llvm/test/CodeGen/ARM/smlad7.ll
index b8e54e6e223..76c7d676f69 100644
--- a/llvm/test/CodeGen/ARM/smlad7.ll
+++ b/llvm/test/CodeGen/ARM/smlad7.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
 ;
 ; Alias check: check that the rewrite isn't triggered when there's a store
 ; aliasing one of the mul load operands. Arguments are now annotated with
diff --git a/llvm/test/CodeGen/ARM/smlad8.ll b/llvm/test/CodeGen/ARM/smlad8.ll
index 0fd75e6fa7d..6c35685f558 100644
--- a/llvm/test/CodeGen/ARM/smlad8.ll
+++ b/llvm/test/CodeGen/ARM/smlad8.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
 ;
 ; Mul with operands that are not simple load and sext/zext chains: this is not
 ; yet supported so the rewrite shouldn't trigger (but we do want to support this
diff --git a/llvm/test/CodeGen/ARM/smlad9.ll b/llvm/test/CodeGen/ARM/smlad9.ll
index 7ae5965ea89..ac88adc2662 100644
--- a/llvm/test/CodeGen/ARM/smlad9.ll
+++ b/llvm/test/CodeGen/ARM/smlad9.ll
@@ -1,4 +1,4 @@
-; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -parallel-dsp -S | FileCheck %s
+; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
 ;
 ; Muls with operands that are constants: not yet supported, so the rewrite
 ; should not trigger (but we do want to add this soon).