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* [x86] add tests for extract/extract/unpack; NFCSanjay Patel2019-01-271-0/+255
| | | | llvm-svn: 352331
* [X86][SSE] Add UNDEF handling to combineSelect ISD::USUBSAT matching (PR40083)Simon Pilgrim2019-01-271-30/+7
| | | | llvm-svn: 352330
* [X86][SSE] Add UNDEF test case for combineSelect ISD::USUBSAT matching (PR40083)Simon Pilgrim2019-01-271-0/+45
| | | | llvm-svn: 352329
* [X86][SSE] Permit UNDEFs in combineAddToSUBUS matching (PR40083)Simon Pilgrim2019-01-271-28/+6
| | | | llvm-svn: 352328
* [x86] add more tests for lowerShuffleWithUndefHalf; NFCSanjay Patel2019-01-271-0/+90
| | | | | | | Some other transform is creating the opposite form and causing an infinite loop if we try to split some of these. llvm-svn: 352327
* [X86][SSE] Add PSUBUS undef element test case (PR40083)Simon Pilgrim2019-01-271-0/+44
| | | | llvm-svn: 352326
* [X86] Add test cases for PR36721 (unnecessary andl for %cl when shifting)Simon Pilgrim2019-01-271-0/+52
| | | | llvm-svn: 352321
* GlobalISel: Verify load/store has a pointer inputMatt Arsenault2019-01-2714-61/+38
| | | | | | | I expected this to be automatically verified, but it seems nothing uses that the type index was declared as a "ptype" llvm-svn: 352319
* [X86][NFC] Replace "<%s" with "< %s" in run-lines.Roman Lebedev2019-01-278-11/+11
| | | | | | | | While i have no intention of actually commiting regeneration of the check lines in these test files with update_llc_test_checks, lack of that whitespace breaks that util, which is mildly inconvenient. llvm-svn: 352318
* [X86] Add CGP tests for PR40486Simon Pilgrim2019-01-271-0/+254
| | | | llvm-svn: 352316
* [X86] Regenerate reverse branch test to explicitly show branching and ↵Simon Pilgrim2019-01-271-7/+138
| | | | | | condition codes. llvm-svn: 352314
* [X86] Regenerate test to explicitly show branching and condition codes.Simon Pilgrim2019-01-271-29/+98
| | | | llvm-svn: 352313
* Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload""Amara Emerson2019-01-271-0/+23
| | | | | | | I reverted it originally due to a bot failing. The underlying bug has been fixed as of r352311. llvm-svn: 352312
* [AArch64][GlobalISel] Fix the G_EXTLOAD combiner creating non-extending ↵Amara Emerson2019-01-272-1/+40
| | | | | | | | | | | | | illegal instructions. This fixes loads like 's1 = load %p (load 1 from %p)' being combined with an extend into an illegal 's8 = g_extload %p (load 1 from %p)' which doesn't do any extension, by avoiding touching those < s8 size loads. This bug was uncovered by a verifier update r351584, which I reverted it to keep the bots green. llvm-svn: 352311
* [X86] Add some missing blsr patternsGabor Buella2019-01-271-8/+3
| | | | | | | | | | | | | | | | | | The add+and sequence followed by a branch can happen e.g. when looping over the set bits of an integer: ``` while (x != 0) { func(x & ~x); x &= x - 1; } ``` Reviewed By: ctopper Differential Revision: https://reviews.llvm.org/D57296 llvm-svn: 352306
* [NFC][X86] Add a few more blsr test casesGabor Buella2019-01-271-0/+100
| | | | llvm-svn: 352305
* [X86] Add a pattern for (i64 (and (anyext def32:), 0x00000000FFFFFFFF)) to ↵Craig Topper2019-01-271-1/+0
| | | | | | | | | | produce SUBREG_TO_REG def32 here means the producing instruction zeroed bits 63:32. We already do this for zext, but it looks like we can get an and+anyext sometimes. Spotted in the diffs from D33587. llvm-svn: 352303
* GlobalISel: Implement narrowScalar for mulMatt Arsenault2019-01-271-0/+26
| | | | llvm-svn: 352300
* GlobalISel: fewerElementsVector for intrinsic_trunc/intrinsic_roundMatt Arsenault2019-01-272-8/+92
| | | | llvm-svn: 352298
* [GlobalISel][IRTranslator] Fix crash on translation of fneg.Amara Emerson2019-01-261-0/+10
| | | | | | | When the fneg IR instruction was added the code to do translation wasn't tested, and tried to get an invalid operand. llvm-svn: 352296
* AMDGPU/GlobalISel: Legalize more bit opsMatt Arsenault2019-01-263-24/+567
| | | | llvm-svn: 352295
* AMDGPU/GlobalISel: Widen small uaddo/usuboMatt Arsenault2019-01-262-0/+194
| | | | llvm-svn: 352294
* [X86] combineCarryThroughADD - add support for X86::COND_A commutations ↵Simon Pilgrim2019-01-261-7/+3
| | | | | | | | | | (PR24545) As discussed on PR24545, we should try to commute X86::COND_A 'icmp ugt' cases to X86::COND_B 'icmp ult' to more optimally bind the carry flag output to a SBB instruction. Differential Revision: https://reviews.llvm.org/D57281 llvm-svn: 352289
* [X86] Fold X86ISD::SBB(ISD::SUB(X,Y),0) -> X86ISD::SBB(X,Y) (PR25858)Simon Pilgrim2019-01-261-9/+6
| | | | | | | | | | We often generate X86ISD::SBB(X, 0) for carry flag arithmetic. I had tried to create test cases for the ADC equivalent (which often uses the same pattern) but haven't managed to find anything yet. Differential Revision: https://reviews.llvm.org/D57169 llvm-svn: 352288
* Generate test results for combine-fcopysign.ll using ↵Amaury Sechet2019-01-261-11/+12
| | | | | | update_llc_test_checks.py . NFC llvm-svn: 352285
* [X86][SSE] Generalized unsigned compares to support nonsplat constant ↵Simon Pilgrim2019-01-262-8/+4
| | | | | | vectors (PR39859) llvm-svn: 352283
* [X86] Add nonsplat increment/decrement constant vector with min/max test ↵Simon Pilgrim2019-01-261-0/+27
| | | | | | (PR39859) llvm-svn: 352281
* [X86] Add test case from PR34292Simon Pilgrim2019-01-261-0/+57
| | | | llvm-svn: 352274
* [X86] Add 'less_than_ideal' followup test case from PR24545Simon Pilgrim2019-01-261-0/+35
| | | | llvm-svn: 352272
* [X86] Autoupgrade some of the intrinsics used by stack folding tests that ↵Craig Topper2019-01-265-93/+96
| | | | | | have been previously removed. llvm-svn: 352271
* [X86] Remove and autoupgrade vpconflict intrinsics that take a mask and ↵Craig Topper2019-01-264-53/+356
| | | | | | | | passthru argument. We have unmasked versions as of r352172 llvm-svn: 352270
* Revert r352255 "[SelectionDAG][X86] Don't use SEXTLOAD for promoting masked ↵Craig Topper2019-01-261-4/+4
| | | | | | | | loads in the type legalizer" This might be breaking an lldb windows buildbot. llvm-svn: 352268
* [X86] Remove GCCBuiltins from 512-bit cvt(u)qqtops, cvt(u)qqtopd, and ↵Craig Topper2019-01-266-40/+252
| | | | | | | | | | | | | | | | cvt(u)dqtops intrinsics. Add new variadic uitofp/sitofp with rounding mode intrinsics. Summary: See clang patch D56998 for a full description. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D56999 llvm-svn: 352266
* GlobalISel: Fix address space limit in LLTMatt Arsenault2019-01-261-0/+26
| | | | | | | | | | | | The IR enforced limit for the address space is 24-bits, but LLT was only using 23-bits. Additionally, the argument to the constructor was truncating to 16-bits. A similar problem still exists for the number of vector elements. The IR enforces no limit, so if you try to use a vector with > 65535 elements the IRTranslator asserts in the LLT constructor. llvm-svn: 352264
* [X86] Add DAG combine to merge vzext_movl with the various fp<->int ↵Craig Topper2019-01-262-28/+0
| | | | | | | | | | | | | | | | conversion operations that only write the lower 64-bits of an xmm register and zero the rest. Summary: We have isel patterns for this, but we're missing some load patterns and all broadcast patterns. A DAG combine seems like a better fit for this. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D56971 llvm-svn: 352260
* [NVPTX] Some nvvm.read.ptx.sreg intrinsics should have ↵Artem Belevich2019-01-261-0/+41
| | | | | | | | | | | | IntrInaccessibleMemOnly attribute. These intrinsics may return different values every time they are called and should not be CSE'd. IntrInaccessibleMemOnly appears to be the right attribute to model this behavior. Differential Revision: https://reviews.llvm.org/D57259 llvm-svn: 352256
* [SelectionDAG][X86] Don't use SEXTLOAD for promoting masked loads in the ↵Craig Topper2019-01-261-4/+4
| | | | | | | | | | | | | | | | | | | | | type legalizer Summary: I'm not sure why we were using SEXTLOAD. EXTLOAD seems more appropriate since we don't care about the upper bits. This patch changes this and then modifies the X86 post legalization combine to emit a extending shuffle instead of a sign_extend_vector_inreg. Could maybe use an any_extend_vector_inreg, but I just did what we already do in LowerLoad. I think we can actually get rid of this code entirely if we switch to -x86-experimental-vector-widening-legalization. On AVX512 targets I think we might be able to use a masked vpmovzx and not have to expand this at all. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D57186 llvm-svn: 352255
* [RISCV] Add target DAG combine for bitcast fabs/fneg on RV32FDAlex Bradbury2019-01-253-39/+33
| | | | | | | | | | | | | DAGCombiner::visitBITCAST will perform: fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) As shown in double-bitmanip-dagcombines.ll, this can be advantageous. But RV32FD doesn't use bitcast directly (as i64 isn't a legal type), and instead uses RISCVISD::SplitF64. This patch adds an equivalent DAG combine for SplitF64. llvm-svn: 352247
* [llvm] Opt-in flag for X86DiscriminateMemOpsMircea Trofin2019-01-254-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently, if an instruction with a memory operand has no debug information, X86DiscriminateMemOps will generate one based on the first line of the enclosing function, or the last seen debug info. This may cause confusion in certain debugging scenarios. The long term approach would be to use the line number '0' in such cases, however, that brings in challenges: the base discriminator value range is limited (4096 values). For the short term, adding an opt-in flag for this feature. See bug 40319 (https://bugs.llvm.org/show_bug.cgi?id=40319) Reviewers: dblaikie, jmorse, gbedwell Reviewed By: dblaikie Subscribers: aprantl, eraman, hiraditya Differential Revision: https://reviews.llvm.org/D57257 llvm-svn: 352246
* [RISCV] Add another potential combine to {double,float}-bitmanip-dagcombines.llAlex Bradbury2019-01-252-1/+103
| | | | | | | | (fcopysign a, (fneg b)) will be expanded to bitwise operations by DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN if the floating point type isn't legal. Arguably it might be worth doing a combine even if it is legal. llvm-svn: 352240
* Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUIAna Pazos2019-01-259-2139/+1584
| | | | | | This reapplies commit r352010 with RISC-V test fixes. llvm-svn: 352237
* [MBP] Don't move bottom block before header if it can't reduce taken branchesGuozhi Wei2019-01-256-37/+70
| | | | | | | | | | | | | | | | | | If bottom of block BB has only one successor OldTop, in most cases it is profitable to move it before OldTop, except the following case: -->OldTop<- | . | | . | | . | ---Pred | | | BB----- Move BB before OldTop can't reduce the number of taken branches, this patch detects this case and prevent the moving. Differential Revision: https://reviews.llvm.org/D57067 llvm-svn: 352236
* [X86] Combine masked store and truncate into masked truncating stores.Craig Topper2019-01-253-159/+114
| | | | | | | | | | We also need to combine to masked truncating with saturation stores, but I'm leaving that for a future patch. This does regress some tests that used truncate wtih saturation followed by a masked store. Those now use a truncating store and use min/max to saturate. Differential Revision: https://reviews.llvm.org/D57218 llvm-svn: 352230
* [RISCV][NFC] s/f32/f64 in double-arith.llAlex Bradbury2019-01-251-11/+11
| | | | | | | The intrinsic names erroneously used the .f32 variant. As the return and argument types were still double the intrinsics calls worked properly. llvm-svn: 352211
* [X86] Simplify X86ISD::ADD/SUB if we don't use the result flagSimon Pilgrim2019-01-253-15/+5
| | | | | | | | | | | | Simplify to the generic ISD::ADD/SUB if we don't make use of the result flag. This mainly helps with ADDCARRY/SUBBORROW intrinsics which get expanded to X86ISD::ADD/SUB but could be simplified further. Noticed in some of the test cases in PR31754 Differential Revision: https://reviews.llvm.org/D57234 llvm-svn: 352210
* [x86] narrow a shuffle that doesn't use or set any high elementsSanjay Patel2019-01-2519-1342/+1359
| | | | | | | | | | | | | | | This isn't the final fix for our reduction/horizontal codegen, but it takes care of a lot of the problems. After we narrow the shuffle, existing combines for insert/extract and binops kick in, and we end up with cheaper 128-bit ops. The avg and mul reduction tests show an existing shuffle lowering hole for AVX2/AVX512. I think in its most minimal form this is: https://bugs.llvm.org/show_bug.cgi?id=40434 ...but we might need multiple fixes to get it right. Differential Revision: https://reviews.llvm.org/D57156 llvm-svn: 352209
* [RISCV] Add tests to demonstrate bitcasted fneg/fabs dagcombinesAlex Bradbury2019-01-253-25/+162
| | | | | | | | | This target-independent code won't trigger for cases such as RV32FD where custom SelectionDAG nodes are generated. These new tests demonstrate such cases. Additionally, float-arith.ll was updated so that fneg.s, fsgnjn.s, and fabs.s selection patterns are actually exercised. llvm-svn: 352199
* [X86] Add addcarry/subborrow combine testsSimon Pilgrim2019-01-251-0/+74
| | | | | | Show failure to simplify cases with zero op/flags llvm-svn: 352196
* [ARM GlobalISel] Support shifts for Thumb2Diana Picus2019-01-256-518/+596
| | | | | | | | | | Same as ARM. On this occasion we split some of the instruction select tests for more complicated instructions into their own files, so we can reuse them for ARM and Thumb mode. Likewise for the legalizer tests. llvm-svn: 352188
* [MSP430] Fix absolute addressing mode printing in AsmPrinterAnton Korobeynikov2019-01-251-0/+15
| | | | | | | | | | | | | Align checks for absolute addressing mode with its current implementation (SR is used as a base register). This fixes https://bugs.llvm.org/show_bug.cgi?id=39993 Patch by Kristina Bessonova! Differential Revision: https://reviews.llvm.org/D56785 llvm-svn: 352178
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