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authorArtem Belevich <tra@google.com>2019-01-26 00:28:32 +0000
committerArtem Belevich <tra@google.com>2019-01-26 00:28:32 +0000
commitdfad526943747238946fb6872016b947869f3fe4 (patch)
treef5e9dd3ff5c4d374236e4e555337fe926e14612a /llvm/test/CodeGen
parentb1d3457c0321a1b04bdd192c6de203f30f682be2 (diff)
downloadbcm5719-llvm-dfad526943747238946fb6872016b947869f3fe4.tar.gz
bcm5719-llvm-dfad526943747238946fb6872016b947869f3fe4.zip
[NVPTX] Some nvvm.read.ptx.sreg intrinsics should have IntrInaccessibleMemOnly attribute.
These intrinsics may return different values every time they are called and should not be CSE'd. IntrInaccessibleMemOnly appears to be the right attribute to model this behavior. Differential Revision: https://reviews.llvm.org/D57259 llvm-svn: 352256
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/NVPTX/intrinsics.ll41
1 files changed, 41 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/NVPTX/intrinsics.ll b/llvm/test/CodeGen/NVPTX/intrinsics.ll
index 668de8a994b..4abbfcbd518 100644
--- a/llvm/test/CodeGen/NVPTX/intrinsics.ll
+++ b/llvm/test/CodeGen/NVPTX/intrinsics.ll
@@ -94,6 +94,43 @@ define i32 @test_popc16_to_32(i16 %a) {
ret i32 %zext
}
+; Most of nvvm.read.ptx.sreg.* intrinsics always return the same value and may
+; be CSE'd.
+; CHECK-LABEL: test_tid
+define i32 @test_tid() {
+; CHECK: mov.u32 %r{{.*}}, %tid.x;
+ %a = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
+; CHECK-NOT: mov.u32 %r{{.*}}, %tid.x;
+ %b = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
+ %ret = add i32 %a, %b
+; CHECK: ret
+ ret i32 %ret
+}
+
+; reading clock() or clock64() should not be CSE'd as each read may return
+; different value.
+; CHECK-LABEL: test_clock
+define i32 @test_clock() {
+; CHECK: mov.u32 %r{{.*}}, %clock;
+ %a = tail call i32 @llvm.nvvm.read.ptx.sreg.clock()
+; CHECK: mov.u32 %r{{.*}}, %clock;
+ %b = tail call i32 @llvm.nvvm.read.ptx.sreg.clock()
+ %ret = add i32 %a, %b
+; CHECK: ret
+ ret i32 %ret
+}
+
+; CHECK-LABEL: test_clock64
+define i64 @test_clock64() {
+; CHECK: mov.u64 %r{{.*}}, %clock64;
+ %a = tail call i64 @llvm.nvvm.read.ptx.sreg.clock64()
+; CHECK: mov.u64 %r{{.*}}, %clock64;
+ %b = tail call i64 @llvm.nvvm.read.ptx.sreg.clock64()
+ %ret = add i64 %a, %b
+; CHECK: ret
+ ret i64 %ret
+}
+
declare float @llvm.fabs.f32(float)
declare double @llvm.fabs.f64(double)
declare float @llvm.nvvm.sqrt.f(float)
@@ -103,3 +140,7 @@ declare i64 @llvm.bitreverse.i64(i64)
declare i16 @llvm.ctpop.i16(i16)
declare i32 @llvm.ctpop.i32(i32)
declare i64 @llvm.ctpop.i64(i64)
+
+declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
+declare i32 @llvm.nvvm.read.ptx.sreg.clock()
+declare i64 @llvm.nvvm.read.ptx.sreg.clock64()
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