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* [X86][SSE] Added extra extractelement testsSimon Pilgrim2016-05-151-29/+288
| | | | | | | | | | Added constant index tests for all 256-bit integer vector types (touching lower / upper 128-bits) Added variable index tests for all 256-bit integer vector types Added out-of-range index tests for all 256-bit integer vector types llvm-svn: 269600
* [X86][SSE] Regenerate extractelement testsSimon Pilgrim2016-05-151-22/+98
| | | | | | Added SSE2/AVX2 target tests llvm-svn: 269595
* [AVX512] Make the permd intrinsics take a 32-bit immediate to match the ↵Craig Topper2016-05-142-20/+20
| | | | | | software spec. llvm-svn: 269579
* ARM: support export directives for WindowsSaleem Abdulrasool2016-05-141-0/+75
| | | | | | | | | | It seems that cl will emit the export directives for Windows ARM targets. The fact that it did this had originally been missed and this functionality was never implemented. This makes it possible to rely solely on the source code for indicating what the exported interfaces are and brings us more compatibility with cl. llvm-svn: 269574
* Fixed lowering of _comi_ intrinsics from all sets - SSE/SSE2/AVX/AVX-512Elena Demikhovsky2016-05-144-135/+174
| | | | | | Differential revision http://reviews.llvm.org/D19261 llvm-svn: 269569
* Revert "[llc] New diagnostic handler"Renato Golin2016-05-1427-32/+32
| | | | | | | | | | | | This reverts commit r269563. Even though now it passes all LLDB bots after a local fix, there's a new buildbot it fails with tests that we hadn't seen locally: http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules/builds/15647 Adding those tests to the list to investigate. llvm-svn: 269568
* Revert changes after test commit.Dima Stepanov2016-05-141-0/+1
| | | | llvm-svn: 269564
* [llc] New diagnostic handlerRenato Golin2016-05-1427-32/+32
| | | | | | | | | | | | | | | | | | | | | | Without a diagnostic handler installed, llc's behaviour is to exit on the first error that it encounters. This is very different from the behaviour of clang and other front ends, which try to gather as many errors as possible before exiting. This commit adds a diagnostic handler to llc, allowing it to find and report more than one error. The old behaviour is preserved under a flag (-exit-on-error). Some of the tests fail with the new diagnostic handler, so they have to use the new flag in order to run under the previous behaviour. Some of these are known bugs, others need further investigation. Ideally, we should fix the tests and remove the flag at some point in the future. Reapplied after fixing the LLDB build that was broken due to the new DiagnosticSeverity in LLVMContext.h. Patch by Diana Picus. llvm-svn: 269563
* [mips] Enable IAS by default for 32-bit MIPS targets (O32).Daniel Sanders2016-05-145-31/+91
| | | | | | | | | | | | | | | | | | | Summary: The MIPS IAS can now pass 'ninja check-all', recurse, build a bootable linux kernel, and pass a variety of LNT testing. Unfortunately we can't enable it by default for 64-bit targets yet since the N32 ABI is still very buggy and this also means we can't enable it for N64 either because we can't distinguish between N32 and N64 in the relevant code. Reviewers: vkalintiris Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D18759 Differential Revision: http://reviews.llvm.org/D18761 llvm-svn: 269560
* Test commt: remove a blank line.Dima Stepanov2016-05-141-1/+0
| | | | llvm-svn: 269558
* [WebAssembly] Fix legalization of i128 shifts.Dan Gohman2016-05-141-0/+280
| | | | | | | | compiler-rt/libgcc shift routines expect the shift count to be an i32, so use i32 as the shift count for shifts that are legalized to libcalls. This also reverts r268991, now that the signatures are correct. llvm-svn: 269531
* [AVX512] Fix types for pshufd intrinsics. The immediate is the second ↵Craig Topper2016-05-143-47/+48
| | | | | | | | argument and the mask is the 4th argument. Also move the 128/256 tests to the right test file. Prior to this the immediate was a strange 16-bits and the 512-bit intrinsic couldn't receive the full 16 mask bits it needs. llvm-svn: 269526
* AMDGPU/R600: Fold global address operandJan Vesely2016-05-131-0/+4
| | | | | | | | | | Reviewers: tstellard Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D19793 llvm-svn: 269480
* AMDGPU/R600: Implement memory loads from constant ASJan Vesely2016-05-132-71/+19
| | | | | | | | | | Reviewers: tstellard Subscribers: arsenm Differential Revision: http://reviews.llvm.org/D19792 llvm-svn: 269479
* ARM: use callee-saved list in the order they're actually saved.Tim Northover2016-05-131-0/+12
| | | | | | | | | When setting the frame pointer, the offset from SP is calculated based on the stack slot it gets allocated, but this slot is in turn based on the order of the CSR list so that list should match the order we actually save the registers in. Mostly it did, but in the edge-case of MachO AAPCS targets it was wrong. llvm-svn: 269459
* [Hexagon] Remove dead nodes from SelectionDAG to avoid cyclesKrzysztof Parzyszek2016-05-131-0/+18
| | | | | | | | Recent changes to the instruction selection code exposed a problem where a dead node was not removed on time. This node had both input and output chains, which lead to an apparent cycle. llvm-svn: 269458
* [AMDGPU] Update nop insertion for debugger usageKonstantin Zhuravlyov2016-05-131-8/+5
| | | | | | | | | - Insert one nop for each high level statement instead of two - Do not insert nop before prologue Differential Revision: http://reviews.llvm.org/D20215 llvm-svn: 269452
* Revert "[ARM,AArch64] NFC. Add extra test cases for bswap lowering."Renato Golin2016-05-132-184/+0
| | | | | | This reverts commit r269425, as it fails on Windows (Thumb only). llvm-svn: 269451
* add support for -print-imm-hex for AArch64Paul Osmialowski2016-05-1339-285/+285
| | | | | | | | | | | | | | | | | | | | | | | | | Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro, but not all of them. Implementation contains following rules: - floating point immediates are always printed as decimal - signed integer immediates are printed depends on flag settings (for negative values 'formatImm' macro prints the value as i.e -0x01 which may be convenient when imm is an address or offset) - logical immediates are always printed as hex - the 64-bit immediate for advSIMD, encoded in "a:b:c:d:e:f:g:h" is always printed as hex - the 64-bit immedaite in exception generation instructions like: brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex - the rest of immediates is printed depends on availability of -print-imm-hex Signed-off-by: Maciej Gabka <maciej.gabka@arm.com> Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com> Differential Revision: http://reviews.llvm.org/D16929 llvm-svn: 269446
* Revert "[llc] New diagnostic handler"Renato Golin2016-05-1327-32/+32
| | | | | | | | This reverts commit r269428, as it breaks the LLDB build. We need to understand how to change LLDB in the same way as LLC before landing this again. llvm-svn: 269432
* [llc] New diagnostic handlerRenato Golin2016-05-1327-32/+32
| | | | | | | | | | | | | | | | | | | Without a diagnostic handler installed, llc's behaviour is to exit on the first error that it encounters. This is very different from the behaviour of clang and other front ends, which try to gather as many errors as possible before exiting. This commit adds a diagnostic handler to llc, allowing it to find and report more than one error. The old behaviour is preserved under a flag (-exit-on-error). Some of the tests fail with the new diagnostic handler, so they have to use the new flag in order to run under the previous behaviour. Some of these are known bugs, others need further investigation. Ideally, we should fix the tests and remove the flag at some point in the future. Patch by Diana Picus. llvm-svn: 269428
* [ARM,AArch64] NFC. Add extra test cases for bswap lowering.Renato Golin2016-05-132-0/+184
| | | | | | | | These tests were sitting in Phab for many months. They're good tests and should be in. Patch by Charlie Turner. llvm-svn: 269425
* [X86][AVX512] Moved CHECKs inside functions to stop update_llc_test_checks ↵Simon Pilgrim2016-05-132-161/+150
| | | | | | | | going haywire I'm not going to regenerate these anytime soon but do have some diffs to apply that I'd like to do with update_llc_test_checks llvm-svn: 269420
* Assure calling "cld" instruction in prologue of X86 interrupt handler function.Amjad Aboud2016-05-131-0/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D18725 llvm-svn: 269413
* AMDGPU: Remove verifier check for scc live insMatt Arsenault2016-05-131-6/+44
| | | | | | | | | | We only really need this to be true for SIFixSGPRCopies. I'm not sure there's any way this could happen before that point. Fixes a case where MachineCSE could introduce a cross block scc use. llvm-svn: 269391
* [ARM] Fixup tests to take into account mov translation. NFC.Renato Golin2016-05-121-2/+2
| | | | | | | | | | | | | Alter instances in the test-suite that use immediates that can be represented in the immediate field of a MOV. The reason for doing this is that when the LDR rt,=imm transformation to MOV rt, imm the existing tests do not need to be modified. Required by the patch that fixes PR25722. Patch by Peter Smith. llvm-svn: 269353
* Revert "LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()"Tom Stellard2016-05-121-32/+0
| | | | | | | | This reverts commit r269016 and also the follow-up commit r269020. This patch caused PR27705. llvm-svn: 269344
* Fixed the callee saved registers list for X86 AllRegs calling convention.Amjad Aboud2016-05-121-6/+20
| | | | | | | | | | | | | | | | 32-bit AllRegs: SSE: xmm0-xmm7 AVX: ymm0-ymm7 AVX512: zmm0-zmm7 + k0-k7 64-bit AllRegs: SSE: xmm0-xmm15 AVX: ymm0-ymm15 AVX512: zmm0-zmm31 + k0-k7 Differential Revision: http://reviews.llvm.org/D20142 llvm-svn: 269337
* [Hexagon] Expand VSelect pseudo instructionsKrzysztof Parzyszek2016-05-121-0/+33
| | | | llvm-svn: 269328
* [Hexagon] Properly handle instruction selection of vsplat intrinsicsKrzysztof Parzyszek2016-05-121-0/+10
| | | | llvm-svn: 269312
* minor test clean up /NFCXinliang David Li2016-05-121-5/+4
| | | | llvm-svn: 269308
* [AArch64] Remove command-line option use for testing.Chad Rosier2016-05-121-1/+1
| | | | | | | The EXTR combine has been in tree for over 2 years without complain, so go ahead and remove the option. llvm-svn: 269292
* [SelectionDAG] Attempt to split BITREVERSE vector legalization into BSWAP ↵Simon Pilgrim2016-05-122-2771/+1142
| | | | | | | | | | | | | | and BITREVERSE stages For BITREVERSE, bit shifting/masking every bit in a vector element is a very lengthy procedure. If the input vector type is a whole multiple of bytes wide then we can split this into a BSWAP shuffle stage (to reverse at the byte level) and then a BITREVERSE stage applied to each byte. Most vector capable targets can efficiently BSWAP using shuffles resulting in a considerable reduction in instructions. With this patch targets would only need to implement a target specific vXi8 BITREVERSE implementation to efficiently reverse most legal vector types. Differential Revision: http://reviews.llvm.org/D19978 llvm-svn: 269290
* Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"Hrvoje Varga2016-05-121-4/+0
| | | | | | This reverts commit r269176 as it caused test-suite failure. llvm-svn: 269287
* [WebAssembly] Fast-isel support for calls, arguments, and selects.Dan Gohman2016-05-122-1/+2
| | | | llvm-svn: 269273
* [PowerPC] Fix a DAG replacement bug in PPCTargetLowering::DAGCombineExtBoolTruncHal Finkel2016-05-121-0/+38
| | | | | | | | | | | | | | | While promoting nodes in PPCTargetLowering::DAGCombineExtBoolTrunc, it is possible for one of the nodes to be replaced by another. To make sure we do not visit the deleted nodes, and to make sure we visit the replacement nodes, use a list of HandleSDNodes to track the to-be-promoted nodes during the promotion process. The same fix has been applied to the analogous code in PPCTargetLowering::DAGCombineTruncBoolExt. Fixes PR26985. llvm-svn: 269272
* [Layout] Add a new test case for optimal rotationXinliang David Li2016-05-121-0/+43
| | | | | | Enabled by -force-precise-rotation-cost option llvm-svn: 269267
* AMDGPU: Fix breaking IR on instructions with multiple pointer operandsMatt Arsenault2016-05-123-0/+310
| | | | | | | | | | | | | The promote alloca pass would attempt to promote an alloca with a select, icmp, or phi user, even though the other operand was from a non-promotable source, producing a select on two different pointer types. Only do this if we know that both operands derive from the same alloca. In the future we should be able to relax this to an alloca which will also be promoted. llvm-svn: 269265
* [AArch64] Add support for unscaled narrow stores in getUsefulBitsForUse.Chad Rosier2016-05-121-0/+38
| | | | llvm-svn: 269263
* All llvm.deoptimize declarations must use the same calling conventionSanjoy Das2016-05-122-25/+34
| | | | | | | | | | | | | | | | | This new verifier rule lets us unambigously pick a calling convention when creating a new declaration for `@llvm.experimental.deoptimize.<ty>`. It is also congruent with our lowering strategy -- since all calls to `@llvm.experimental.deoptimize` are lowered to calls to `__llvm_deoptimize`, it is reasonable to enforce a unique calling convention. Some of the tests that were breaking this verifier rule have had to be split up into different .ll files. The inliner was violating this rule as well, and has been fixed to avoid producing invalid IR. llvm-svn: 269261
* Fix a bug when hoist spill to a BB with landingpad successor.Wei Mi2016-05-111-0/+62
| | | | | | | | | | | | | | | This is to fix the bug in https://llvm.org/bugs/show_bug.cgi?id=27612. When spill is hoisted to a BB with landingpad successor, and if the VNI of the spill reg lives into the landingpad successor, the spill should be inserted before the call which may throw exception. InsertPointAnalysis is used to compute the safe insert point. http://reviews.llvm.org/D20027 is a preparing patch for this patch. Differential Revision: http://reviews.llvm.org/D19884. llvm-svn: 269249
* regenerate checksSanjay Patel2016-05-111-4/+13
| | | | llvm-svn: 269241
* [AArch64] Improve getUsefulBitsForUse for narrow stores.Chad Rosier2016-05-111-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For narrow stores (e.g., strb, srth) we know the upper bits of the register are unused/not useful. In some cases we can use this information to eliminate unnecessary instructions. For example, without this patch we generate (from the 2nd test case): ldr w8, [x0] and w8, w8, #0xfff0 bfxil w8, w2, #16, #4 strh w8, [x1] and after the patch the 'and' is removed: ldr w8, [x0] bfxil w8, w2, #16, #4 strh w8, [x1] ret During the lowering of the bitfield insert instruction the 'and' is eliminated because we know the upper 16-bits that are masked off are unused and the lower 4-bits that are masked off are overwritten by the insert itself. Therefore, the 'and' is unnecessary. Differential Revision: http://reviews.llvm.org/D20175 llvm-svn: 269226
* [X86][AVX512] Fixed VPERMILPD/VPERMILPS shuffle comments.Simon Pilgrim2016-05-112-12/+12
| | | | | | Fixed incorrect operands indices used to access src registers llvm-svn: 269221
* AMDGPU: Split private memory testsJan Vesely2016-05-113-24/+57
| | | | | | | | | | Reenable R600 testing reviewer: arsenm Differential Revision: http://reviews.llvm.org/D20031 llvm-svn: 269207
* [WebAssembl] Implement enough of fast-isel to run the comparison tests.Dan Gohman2016-05-112-0/+2
| | | | llvm-svn: 269203
* [X86][AVX512] Regenerate intrinsics testSimon Pilgrim2016-05-112-83/+133
| | | | llvm-svn: 269193
* [Hexagon] Use offsets relative to FP+8 in .cfi_offset instructionsKrzysztof Parzyszek2016-05-111-0/+43
| | | | | | | | When generating .cfi_offset instructions, make sure that the offset is calculated with respect to the register used to define the CFA (which is currently always FP+8). llvm-svn: 269191
* [X86] Regenerate shuffle testSimon Pilgrim2016-05-111-12/+36
| | | | llvm-svn: 269186
* [mips][microMIPS] Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-05-111-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D19713 llvm-svn: 269176
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