[Hexagon] Expand VSelect pseudo instructions

llvm-svn: 269328

1 files changed, 33 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll b/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll
new file mode 100644
index 00000000000..ef86e47e395
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll
@@ -0,0 +1,33 @@
+; RUN: llc -march=hexagon < %s
+; REQUIRES: asserts
+
+target triple = "hexagon"
+
+; Function Attrs: nounwind
+define void @fred() #0 {
+entry:
+  br label %for.body9.us
+
+for.body9.us:
+  %cmp10.us = icmp eq i32 0, undef
+  %.h63h32.2.us = select i1 %cmp10.us, <16 x i32> zeroinitializer, <16 x i32> undef
+  %0 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %.h63h32.2.us, <16 x i32> undef, i32 2)
+  %1 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1> undef, <16 x i32> undef, <16 x i32> %0)
+  %2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %1)
+  %3 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %2, i32 62)
+  %4 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %3)
+  store <16 x i32> %4, <16 x i32>* undef, align 64
+  br i1 undef, label %for.body9.us, label %for.body43.us.preheader
+
+for.body43.us.preheader:                          ; preds = %for.body9.us
+  ret void
+}
+
+declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
+declare <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1>, <16 x i32>, <16 x i32>) #1
+declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
+declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
+declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }