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* Revert "[ARM,AArch64] NFC. Add extra test cases for bswap lowering."Renato Golin2016-05-132-184/+0
| | | | | | This reverts commit r269425, as it fails on Windows (Thumb only). llvm-svn: 269451
* add support for -print-imm-hex for AArch64Paul Osmialowski2016-05-1339-285/+285
| | | | | | | | | | | | | | | | | | | | | | | | | Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro, but not all of them. Implementation contains following rules: - floating point immediates are always printed as decimal - signed integer immediates are printed depends on flag settings (for negative values 'formatImm' macro prints the value as i.e -0x01 which may be convenient when imm is an address or offset) - logical immediates are always printed as hex - the 64-bit immediate for advSIMD, encoded in "a:b:c:d:e:f:g:h" is always printed as hex - the 64-bit immedaite in exception generation instructions like: brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex - the rest of immediates is printed depends on availability of -print-imm-hex Signed-off-by: Maciej Gabka <maciej.gabka@arm.com> Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com> Differential Revision: http://reviews.llvm.org/D16929 llvm-svn: 269446
* Revert "[llc] New diagnostic handler"Renato Golin2016-05-1327-32/+32
| | | | | | | | This reverts commit r269428, as it breaks the LLDB build. We need to understand how to change LLDB in the same way as LLC before landing this again. llvm-svn: 269432
* [llc] New diagnostic handlerRenato Golin2016-05-1327-32/+32
| | | | | | | | | | | | | | | | | | | Without a diagnostic handler installed, llc's behaviour is to exit on the first error that it encounters. This is very different from the behaviour of clang and other front ends, which try to gather as many errors as possible before exiting. This commit adds a diagnostic handler to llc, allowing it to find and report more than one error. The old behaviour is preserved under a flag (-exit-on-error). Some of the tests fail with the new diagnostic handler, so they have to use the new flag in order to run under the previous behaviour. Some of these are known bugs, others need further investigation. Ideally, we should fix the tests and remove the flag at some point in the future. Patch by Diana Picus. llvm-svn: 269428
* [ARM,AArch64] NFC. Add extra test cases for bswap lowering.Renato Golin2016-05-132-0/+184
| | | | | | | | These tests were sitting in Phab for many months. They're good tests and should be in. Patch by Charlie Turner. llvm-svn: 269425
* [X86][AVX512] Moved CHECKs inside functions to stop update_llc_test_checks ↵Simon Pilgrim2016-05-132-161/+150
| | | | | | | | going haywire I'm not going to regenerate these anytime soon but do have some diffs to apply that I'd like to do with update_llc_test_checks llvm-svn: 269420
* Assure calling "cld" instruction in prologue of X86 interrupt handler function.Amjad Aboud2016-05-131-0/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D18725 llvm-svn: 269413
* AMDGPU: Remove verifier check for scc live insMatt Arsenault2016-05-131-6/+44
| | | | | | | | | | We only really need this to be true for SIFixSGPRCopies. I'm not sure there's any way this could happen before that point. Fixes a case where MachineCSE could introduce a cross block scc use. llvm-svn: 269391
* [ARM] Fixup tests to take into account mov translation. NFC.Renato Golin2016-05-121-2/+2
| | | | | | | | | | | | | Alter instances in the test-suite that use immediates that can be represented in the immediate field of a MOV. The reason for doing this is that when the LDR rt,=imm transformation to MOV rt, imm the existing tests do not need to be modified. Required by the patch that fixes PR25722. Patch by Peter Smith. llvm-svn: 269353
* Revert "LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()"Tom Stellard2016-05-121-32/+0
| | | | | | | | This reverts commit r269016 and also the follow-up commit r269020. This patch caused PR27705. llvm-svn: 269344
* Fixed the callee saved registers list for X86 AllRegs calling convention.Amjad Aboud2016-05-121-6/+20
| | | | | | | | | | | | | | | | 32-bit AllRegs: SSE: xmm0-xmm7 AVX: ymm0-ymm7 AVX512: zmm0-zmm7 + k0-k7 64-bit AllRegs: SSE: xmm0-xmm15 AVX: ymm0-ymm15 AVX512: zmm0-zmm31 + k0-k7 Differential Revision: http://reviews.llvm.org/D20142 llvm-svn: 269337
* [Hexagon] Expand VSelect pseudo instructionsKrzysztof Parzyszek2016-05-121-0/+33
| | | | llvm-svn: 269328
* [Hexagon] Properly handle instruction selection of vsplat intrinsicsKrzysztof Parzyszek2016-05-121-0/+10
| | | | llvm-svn: 269312
* minor test clean up /NFCXinliang David Li2016-05-121-5/+4
| | | | llvm-svn: 269308
* [AArch64] Remove command-line option use for testing.Chad Rosier2016-05-121-1/+1
| | | | | | | The EXTR combine has been in tree for over 2 years without complain, so go ahead and remove the option. llvm-svn: 269292
* [SelectionDAG] Attempt to split BITREVERSE vector legalization into BSWAP ↵Simon Pilgrim2016-05-122-2771/+1142
| | | | | | | | | | | | | | and BITREVERSE stages For BITREVERSE, bit shifting/masking every bit in a vector element is a very lengthy procedure. If the input vector type is a whole multiple of bytes wide then we can split this into a BSWAP shuffle stage (to reverse at the byte level) and then a BITREVERSE stage applied to each byte. Most vector capable targets can efficiently BSWAP using shuffles resulting in a considerable reduction in instructions. With this patch targets would only need to implement a target specific vXi8 BITREVERSE implementation to efficiently reverse most legal vector types. Differential Revision: http://reviews.llvm.org/D19978 llvm-svn: 269290
* Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"Hrvoje Varga2016-05-121-4/+0
| | | | | | This reverts commit r269176 as it caused test-suite failure. llvm-svn: 269287
* [WebAssembly] Fast-isel support for calls, arguments, and selects.Dan Gohman2016-05-122-1/+2
| | | | llvm-svn: 269273
* [PowerPC] Fix a DAG replacement bug in PPCTargetLowering::DAGCombineExtBoolTruncHal Finkel2016-05-121-0/+38
| | | | | | | | | | | | | | | While promoting nodes in PPCTargetLowering::DAGCombineExtBoolTrunc, it is possible for one of the nodes to be replaced by another. To make sure we do not visit the deleted nodes, and to make sure we visit the replacement nodes, use a list of HandleSDNodes to track the to-be-promoted nodes during the promotion process. The same fix has been applied to the analogous code in PPCTargetLowering::DAGCombineTruncBoolExt. Fixes PR26985. llvm-svn: 269272
* [Layout] Add a new test case for optimal rotationXinliang David Li2016-05-121-0/+43
| | | | | | Enabled by -force-precise-rotation-cost option llvm-svn: 269267
* AMDGPU: Fix breaking IR on instructions with multiple pointer operandsMatt Arsenault2016-05-123-0/+310
| | | | | | | | | | | | | The promote alloca pass would attempt to promote an alloca with a select, icmp, or phi user, even though the other operand was from a non-promotable source, producing a select on two different pointer types. Only do this if we know that both operands derive from the same alloca. In the future we should be able to relax this to an alloca which will also be promoted. llvm-svn: 269265
* [AArch64] Add support for unscaled narrow stores in getUsefulBitsForUse.Chad Rosier2016-05-121-0/+38
| | | | llvm-svn: 269263
* All llvm.deoptimize declarations must use the same calling conventionSanjoy Das2016-05-122-25/+34
| | | | | | | | | | | | | | | | | This new verifier rule lets us unambigously pick a calling convention when creating a new declaration for `@llvm.experimental.deoptimize.<ty>`. It is also congruent with our lowering strategy -- since all calls to `@llvm.experimental.deoptimize` are lowered to calls to `__llvm_deoptimize`, it is reasonable to enforce a unique calling convention. Some of the tests that were breaking this verifier rule have had to be split up into different .ll files. The inliner was violating this rule as well, and has been fixed to avoid producing invalid IR. llvm-svn: 269261
* Fix a bug when hoist spill to a BB with landingpad successor.Wei Mi2016-05-111-0/+62
| | | | | | | | | | | | | | | This is to fix the bug in https://llvm.org/bugs/show_bug.cgi?id=27612. When spill is hoisted to a BB with landingpad successor, and if the VNI of the spill reg lives into the landingpad successor, the spill should be inserted before the call which may throw exception. InsertPointAnalysis is used to compute the safe insert point. http://reviews.llvm.org/D20027 is a preparing patch for this patch. Differential Revision: http://reviews.llvm.org/D19884. llvm-svn: 269249
* regenerate checksSanjay Patel2016-05-111-4/+13
| | | | llvm-svn: 269241
* [AArch64] Improve getUsefulBitsForUse for narrow stores.Chad Rosier2016-05-111-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For narrow stores (e.g., strb, srth) we know the upper bits of the register are unused/not useful. In some cases we can use this information to eliminate unnecessary instructions. For example, without this patch we generate (from the 2nd test case): ldr w8, [x0] and w8, w8, #0xfff0 bfxil w8, w2, #16, #4 strh w8, [x1] and after the patch the 'and' is removed: ldr w8, [x0] bfxil w8, w2, #16, #4 strh w8, [x1] ret During the lowering of the bitfield insert instruction the 'and' is eliminated because we know the upper 16-bits that are masked off are unused and the lower 4-bits that are masked off are overwritten by the insert itself. Therefore, the 'and' is unnecessary. Differential Revision: http://reviews.llvm.org/D20175 llvm-svn: 269226
* [X86][AVX512] Fixed VPERMILPD/VPERMILPS shuffle comments.Simon Pilgrim2016-05-112-12/+12
| | | | | | Fixed incorrect operands indices used to access src registers llvm-svn: 269221
* AMDGPU: Split private memory testsJan Vesely2016-05-113-24/+57
| | | | | | | | | | Reenable R600 testing reviewer: arsenm Differential Revision: http://reviews.llvm.org/D20031 llvm-svn: 269207
* [WebAssembl] Implement enough of fast-isel to run the comparison tests.Dan Gohman2016-05-112-0/+2
| | | | llvm-svn: 269203
* [X86][AVX512] Regenerate intrinsics testSimon Pilgrim2016-05-112-83/+133
| | | | llvm-svn: 269193
* [Hexagon] Use offsets relative to FP+8 in .cfi_offset instructionsKrzysztof Parzyszek2016-05-111-0/+43
| | | | | | | | When generating .cfi_offset instructions, make sure that the offset is calculated with respect to the register used to define the CFA (which is currently always FP+8). llvm-svn: 269191
* [X86] Regenerate shuffle testSimon Pilgrim2016-05-111-12/+36
| | | | llvm-svn: 269186
* [mips][microMIPS] Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-05-111-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D19713 llvm-svn: 269176
* [AArch64] Fix DAG selection for cmps for fp16 typeWeiming Zhao2016-05-111-0/+12
| | | | | | | | | | | | Summary: When emitting comparison for fp16, in addition to promote the LHS and RHS to fp32, we need to change the VT as well. Reviewers: t.p.northover Subscribers: t.p.northover, aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D19922 llvm-svn: 269151
* AMDGPU: Change private_element_size to 4Matt Arsenault2016-05-117-41/+81
| | | | llvm-svn: 269145
* auto-generate checksSanjay Patel2016-05-101-21/+68
| | | | llvm-svn: 269134
* AArch64: allow vN to represent 64-bit registers in inline asm.Tim Northover2016-05-101-0/+14
| | | | | | | | Unlike xN/wN, the size of vN is genuinely ambiguous in the assembly, so we should try to infer what was intended from the type. But only down to 64-bits (vN can never represent sN, hN or bN). llvm-svn: 269132
* remove some comments and other cruft from checksSanjay Patel2016-05-101-19/+15
| | | | llvm-svn: 269128
* update test to use FileCheck for tighter checkingSanjay Patel2016-05-101-8/+114
| | | | llvm-svn: 269123
* update test to use FileCheck for tighter checkingSanjay Patel2016-05-101-3/+17
| | | | llvm-svn: 269122
* [X86] Properly check that EAX is dead when copying EFLAGS.Quentin Colombet2016-05-101-0/+67
| | | | | | | | | | | | This fixes a bug introduced in r267623, where we got smarter and avoided to save EAX before using it. However, we failed to check if any of the subregister of EAX were alive and thus, missed cases where we have to save EAX before using it. The problem may happen on every X86/i386/... platform. This fixes llvm.org/PR27624 llvm-svn: 269115
* ARM: stop emitting blx instructions for most calls on MachO.Tim Northover2016-05-1026-166/+124
| | | | | | | | | | | I'm really not sure why we were in the first place, it's the linker's job to convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls that could be locally resolved completely unencodable since all offsets to BLX are multiples of 4. rdar://26182344 llvm-svn: 269101
* Make "@name =" mandatory for globals in .ll files.Rafael Espindola2016-05-107-40/+40
| | | | | | | | | | | | | | | | | | | | | | | An oddity of the .ll syntax is that the "@var = " in @var = global i32 42 is optional. Writing just global i32 42 is equivalent to @0 = global i32 42 This means that there is a pretty big First set at the top level. The current implementation maintains it manually. I was trying to refactor it, but then started wondering why keep it a all. I personally find the above syntax confusing. It looks like something is missing. This patch removes the feature and simplifies the parser. llvm-svn: 269096
* Fix PR26655: Bail out if all regs of an inst BUNDLE have the correct kill flagMandeep Singh Grang2016-05-101-0/+41
| | | | | | | | | | | | | | | | | | | | Summary: While setting kill flags on instructions inside a BUNDLE, we bail out as soon as we set kill flag on a register. But we are missing a check when all the registers already have the correct kill flag set. We need to bail out in that case as well. This patch refactors the old code and simply makes use of the addRegisterKilled function in MachineInstr.cpp in order to determine whether to set/remove kill on an instruction. Reviewers: apazos, t.p.northover, pete, MatzeB Subscribers: MatzeB, davide, llvm-commits Differential Revision: http://reviews.llvm.org/D17356 llvm-svn: 269092
* [WebAssembly] Preliminary fast-isel support.Dan Gohman2016-05-108-5/+38
| | | | llvm-svn: 269083
* [X86][AVX512] Added another masked shuffle combine from load testSimon Pilgrim2016-05-101-0/+13
| | | | llvm-svn: 269077
* [ScheduleDAG] Make sure to process all def operands before any use operandsKrzysztof Parzyszek2016-05-101-0/+20
| | | | | | | | | | | | | | | | | An example from Hexagon where things went wrong: %R0<def> = L2_loadrigp <ga:@fp04> ; load function address J2_callr %R0<kill>, ..., %R0<imp-def> ; call *R0, return value in R0 ScheduleDAGInstrs::buildSchedGraph would visit all instructions going backwards, and in each instruction it would visit all operands in their order on the operand list. In the case of this call, it visited the use of R0 first, then removed it from the set Uses after it visited the def. This caused the DAG to be missing the data dependence edge on R0 between the load and the call. Differential Revision: http://reviews.llvm.org/D20102 llvm-svn: 269076
* [PR27599] [SystemZ] [SelectionDAG] Fix extension of atomic cmpxchg result.Marcin Koscielnicki2016-05-101-0/+81
| | | | | | | | | | | | Currently, SelectionDAG assumes 8/16-bit cmpxchg returns either a sign extended result, or a zero extended result. SystemZ takes a third option by returning junk in the high bits (rotated contents of the other bytes in the memory word). In that case, don't use Assert*ext, and zero-extend the result ourselves if a comparison is needed. Differential Revision: http://reviews.llvm.org/D19800 llvm-svn: 269075
* [X86][AVX] Added some shuffle combine from load testsSimon Pilgrim2016-05-102-0/+80
| | | | | | As discussed on D19198 - we need to check what happens when we shuffle with different value type to the load llvm-svn: 269068
* [X86][AVX512] Added masked version of MOVDDUP test with 16f32Simon Pilgrim2016-05-101-0/+20
| | | | llvm-svn: 269038
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